Searched refs:REG_UPDATE_6 (Results 1 – 16 of 16) sorted by relevance
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_opp.c | 123 REG_UPDATE_6(DPG_CONTROL, in opp2_set_disp_pattern_generator()
182 REG_UPDATE_6(DPG_CONTROL, in opp2_set_disp_pattern_generator()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_afmt.c | 76 REG_UPDATE_6(AFMT_60958_2, in afmt3_setup_hdmi_audio()
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| D | dcn30_hubp.c | 355 REG_UPDATE_6(DCSURF_SURFACE_CONTROL, in hubp3_dcc_control_sienna_cichlid()
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| D | dcn30_dio_stream_encoder.c | 621 REG_UPDATE_6(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_opp.c | 121 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
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| D | dcn10_stream_encoder.c | 504 REG_UPDATE_6(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
1322 REG_UPDATE_6(AFMT_60958_2, in enc1_se_setup_hdmi_audio()
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| D | dcn10_mpc.c | 101 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id], in mpc1_update_stereo_mix()
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| D | dcn10_dpp_dscl.c | 305 REG_UPDATE_6(DSCL_2TAP_CONTROL, in dpp1_dscl_set_scl_filter()
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| D | dcn10_hubp.c | 148 REG_UPDATE_6(DCSURF_ADDR_CONFIG, in hubp1_program_tiling()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dio_stream_encoder.c | 174 REG_UPDATE_6(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dio_stream_encoder.c | 141 REG_UPDATE_6(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_hw.c | 324 REG_UPDATE_6(DC_I2C_CONTROL, in setup_engine()
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| D | dce_mem_input.c | 436 REG_UPDATE_6(GRPH_CONTROL, in program_tiling()
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| D | dce_stream_encoder.c | 1332 REG_UPDATE_6(AFMT_60958_2, in dce110_se_setup_hdmi_audio()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 260 #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ macro
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 244 REG_UPDATE_6(OTG_V_TOTAL_CONTROL, in optc3_fpu_set_vrr_m_const()
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