/linux-6.6.21/drivers/net/wireless/ath/ath9k/ |
D | ar9002_calib.c | 111 REG_CLR_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_per_calibration() 456 REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal() 468 REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); in ar9271_hw_pa_cal() 470 REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); in ar9271_hw_pa_cal() 472 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); in ar9271_hw_pa_cal() 474 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); in ar9271_hw_pa_cal() 476 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); in ar9271_hw_pa_cal() 478 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); in ar9271_hw_pa_cal() 531 REG_CLR_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal() 755 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9285_hw_cl_cal() [all …]
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D | ar9003_wow.c | 54 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep() 58 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep() 316 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_WOW_PME_CLR); in ath9k_hw_wow_enable() 389 REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable() 438 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_wow_enable() 449 REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); in ath9k_hw_wow_enable()
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D | ar9002_phy.c | 215 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate() 219 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate() 484 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config() 499 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit); in ar9002_hw_spectral_scan_config() 559 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_start()
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D | ar9003_phy.c | 822 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix() 824 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix() 826 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix() 1148 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control() 1451 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params() 1476 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params() 1640 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity() 1642 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity() 1644 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity() 1646 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity() [all …]
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D | calib.c | 238 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal() 289 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf() 298 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf() 300 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
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D | mac.c | 162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma() 163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma() 164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma() 649 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort() 661 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort() 681 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_startpcureceive() 1021 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
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D | ar9003_calib.c | 349 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection() 351 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_dynamic_osdac_selection() 372 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_dynamic_osdac_selection() 374 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection() 376 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection() 402 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection() 534 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection() 1441 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem() 1468 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_init_cal_pcoem()
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D | hw.c | 740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc() 1286 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode() 1414 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset() 1695 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp() 2102 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep() 2103 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep() 2104 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep() 2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep() 2124 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN); in ath9k_set_power_sleep() 2160 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep() [all …]
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D | rng.c | 33 REG_CLR_BIT(ah, AR_PHY_TEST(ah), AR_PHY_TEST_RX_OBS_SEL_BIT5); in ath9k_rng_data_read()
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D | ar9003_mci.c | 765 REG_CLR_BIT(ah, AR_PHY_TIMING4, in ar9003_mci_end_reset() 819 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, in ar9003_mci_osla_setup() 1017 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_reset() 1141 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch() 1143 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch() 1451 REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1); in ar9003_mci_set_power_awake()
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D | ar9002_hw.c | 252 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave() 377 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
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D | ar9003_paprd.c | 316 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah), in ar9003_get_desired_gain() 815 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah), in ar9003_paprd_setup_gain_table() 935 REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah), in ar9003_paprd_create_curve() 954 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1(ah), in ar9003_paprd_create_curve()
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D | btcoex.c | 176 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_2wire() 331 REG_CLR_BIT(ah, AR_BT_COEX_MODE2, AR_BT_PHY_ERR_BT_COLL_ENABLE); in ath9k_hw_btcoex_enable_3wire()
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D | ar9003_aic.c | 254 REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_start() 509 REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_continue()
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D | ar5008_phy.c | 1026 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new() 1236 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params() 1261 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
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D | hw.h | 129 #define REG_CLR_BIT(_a, _r, _f) \ macro
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D | ar9003_eeprom.c | 3754 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_ant_ctrl_apply() 3758 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()
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