Searched refs:REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR (Results 1 – 2 of 2) sorted by relevance
584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); in a6xx_gmu_rpmh_init()
8053 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 macro