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/linux-6.6.21/Documentation/PCI/
Dpciebus-howto.rst5 The PCI Express Port Bus Driver Guide HOWTO
14 This guide describes the basics of the PCI Express Port Bus driver
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
26 internal logical PCI buses. The Switch Port, which has its secondary
28 switch's Upstream Port. The switch's Downstream Port is bridging from
[all …]
Dpcieaer-howto.rst55 The PCIe AER driver is a Root Port service driver attached
56 via the PCIe Port Bus driver. If a user wants to use it, the driver
85 the error message to the Root Port. Please refer to PCIe specs for other
122 error message to the Root Port above it when it captures
123 an error. The Root Port, upon receiving an error reporting message,
129 Error Command Register, the Root Port generates an interrupt when an
144 fatal error happens. The Root Port AER service driver provides a
147 Upstream Port drivers may provide their own reset_link functions.
185 Endpoint <==> Downstream Port B <==> Upstream Port A <==> Root Port
187 If Upstream Port A captures an AER error, the hierarchy consists of
[all …]
/linux-6.6.21/drivers/usb/serial/
Dio_ionsp.h124 #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))… argument
125 #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) argument
131 #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))… argument
193 #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ argument
195 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \
203 #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ argument
205 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \
/linux-6.6.21/arch/arm/boot/dts/marvell/
Darmada-xp-mv78460.dtsi82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
[all …]
Darmada-xp-mv78260.dtsi65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
[all …]
Darmada-xp-mv78230.dtsi64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
[all …]
Darmada-385.dtsi52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
56 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
58 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
Darmada-380.dtsi53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
Darmada-xp-db.dts192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
/linux-6.6.21/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
107 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
108 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
109 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
110 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
111 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
112 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
[all …]
/linux-6.6.21/drivers/usb/typec/tcpm/
DKconfig4 tristate "USB Type-C Port Controller Manager"
9 The Type-C Port Controller Manager provides a USB PD and USB Type-C
10 state machine for use with Type-C Port Controllers.
15 tristate "Type-C Port Controller Interface driver"
19 Type-C Port Controller driver for TCPCI-compliant controller.
27 Type-C Port Controller Manager to provide USB PD and USB
35 USB Type-C. It works with Type-C Port Controller Manager
43 USB Type-C. It works with Type-C Port Controller Manager
53 with Type-C Port Controller Manager.
63 Type-C Port Controller Manager to provide USB PD and USB
[all …]
/linux-6.6.21/Documentation/driver-api/tty/
Dtty_port.rst4 TTY Port
15 The reference and details are contained in the `TTY Port Reference`_ and `TTY
16 Port Operations Reference`_ sections at the bottom.
18 TTY Port Functions
58 TTY Port Reference
66 TTY Port Operations Reference
/linux-6.6.21/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts208 reg = <0x3>; /* Port */
215 reg = <0x4>; /* Port */
220 reg = <0x5>; /* Port */
225 reg = <0x6>; /* Port */
230 reg = <0x7>; /* Port */
235 reg = <0x8>; /* Port */
240 reg = <0x9>; /* Port */
245 reg = <0xa>; /* Port */
250 reg = <0xb>; /* Port */
255 reg = <0xc>; /* Port */
[all …]
Docteon_68xx.dts269 reg = <0x0>; /* Port */
275 reg = <0x1>; /* Port */
281 reg = <0x2>; /* Port */
287 reg = <0x3>; /* Port */
301 reg = <0x0>; /* Port */
307 reg = <0x1>; /* Port */
313 reg = <0x2>; /* Port */
319 reg = <0x3>; /* Port */
333 reg = <0x0>; /* Port */
339 reg = <0x1>; /* Port */
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/usb/
Donnn,nb7vpq904m.yaml72 - Port A to RX2 lane
73 - Port B to TX2 lane
74 - Port C to TX1 lane
75 - Port D to RX1 lane
83 - Port A to RX1 lane
84 - Port B to TX1 lane
85 - Port C to TX2 lane
86 - Port D to RX2 lane
Dti,hd3ss3220.yaml7 title: TI HD3SS3220 TypeC DRP Port Controller
15 HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a
16 Dual Role Port (DRP) making it ideal for any application.
Dmediatek,mt6370-tcpc.yaml7 title: MediatTek MT6370 Type-C Port Switch and Power Delivery controller
15 regulators (DSV/VIBLDO), and TypeC Port Switch with Power Delivery controller.
16 This document only describes MT6370 Type-C Port Switch and
/linux-6.6.21/Documentation/arch/s390/
Dqeth.rst5 OSA and HiperSockets Bridge Port Support
12 a primary or a secondary Bridge Port. For more information, see
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
30 When run on HiperSockets Bridge Capable Port hardware with host address
39 deregistered on the Bridge Port HiperSockets channel, or address
/linux-6.6.21/drivers/pci/pcie/
DKconfig3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This enables PCI Express Port Bus support. Users can then enable
11 Management Events, and Downstream Port Containment.
33 This enables PCI Express Root Port Advanced Error Reporting
35 Port will be handled by PCI Express AER driver.
42 This enables PCI Express Root Port Advanced Error Reporting
122 bool "PCI Express Downstream Port Containment support"
125 This enables PCI Express Downstream Port Containment (DPC)
145 in the Downstream Port Containment Related Enhancements ECN to
/linux-6.6.21/Documentation/gpu/dp-mst/
Dtopology-figure-1.dot48 port1 [label="Port #1";shape=oval];
49 port2 [label="Port #2";shape=oval];
50 port3 [label="Port #3";shape=oval];
51 port4 [label="Port #4";shape=oval];
Dtopology-figure-2.dot47 port1 [label="Port #1"];
48 port2 [label="Port #2"];
49 port3 [label="Port #3"];
50 port4 [label="Port #4";style=filled;fillcolor=grey];
Dtopology-figure-3.dot50 port1 [label="Port #1"];
51 port2 [label="Port #2";penwidth=5];
52 port3 [label="Port #3";penwidth=3];
53 port4 [label="Port #4";style=filled;fillcolor=grey];
/linux-6.6.21/Documentation/devicetree/bindings/net/
Dcavium-pip.txt62 reg = <0x0>; /* Port */
68 reg = <0x1>; /* Port */
74 reg = <0x2>; /* Port */
80 reg = <0x3>; /* Port */
94 reg = <0x0>; /* Port */
/linux-6.6.21/arch/arc/boot/dts/
Dabilis_tb100.dtsi30 /* Port 1 */
43 /* Port 2 */
56 /* Port 3 */
69 /* Port 4 */
82 /* Port 5 */
95 /* Port 6 */
111 /* Port 7 */
124 /* Port 8 */
128 /* Port 9 */

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