Searched refs:PSB_RVDC32 (Results 1 – 6 of 6) sorted by relevance
130 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB); in oaktrail_save_display_registers()131 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); in oaktrail_save_display_registers()132 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2); in oaktrail_save_display_registers()133 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); in oaktrail_save_display_registers()134 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4); in oaktrail_save_display_registers()135 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5); in oaktrail_save_display_registers()136 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6); in oaktrail_save_display_registers()137 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); in oaktrail_save_display_registers()140 p->conf = PSB_RVDC32(PIPEACONF); in oaktrail_save_display_registers()141 p->src = PSB_RVDC32(PIPEASRC); in oaktrail_save_display_registers()[all …]
747 hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL); in oaktrail_hdmi_save()748 hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL); in oaktrail_hdmi_save()749 hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST); in oaktrail_hdmi_save()750 hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE); in oaktrail_hdmi_save()751 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); in oaktrail_hdmi_save()754 pipeb->conf = PSB_RVDC32(PIPEBCONF); in oaktrail_hdmi_save()755 pipeb->src = PSB_RVDC32(PIPEBSRC); in oaktrail_hdmi_save()756 pipeb->htotal = PSB_RVDC32(HTOTAL_B); in oaktrail_hdmi_save()757 pipeb->hblank = PSB_RVDC32(HBLANK_B); in oaktrail_hdmi_save()758 pipeb->hsync = PSB_RVDC32(HSYNC_B); in oaktrail_hdmi_save()[all …]
114 regs->saveDSPARB = PSB_RVDC32(DSPARB); in psb_save_display_registers()115 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1); in psb_save_display_registers()116 regs->saveDSPFW2 = PSB_RVDC32(DSPFW2); in psb_save_display_registers()117 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3); in psb_save_display_registers()118 regs->saveDSPFW4 = PSB_RVDC32(DSPFW4); in psb_save_display_registers()119 regs->saveDSPFW5 = PSB_RVDC32(DSPFW5); in psb_save_display_registers()120 regs->saveDSPFW6 = PSB_RVDC32(DSPFW6); in psb_save_display_registers()121 regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); in psb_save_display_registers()
53 u32 writeVal = PSB_RVDC32(reg); in gma_enable_pipestat()56 (void) PSB_RVDC32(reg); in gma_enable_pipestat()68 u32 writeVal = PSB_RVDC32(reg); in gma_disable_pipestat()71 (void) PSB_RVDC32(reg); in gma_disable_pipestat()93 pipe_stat_val = PSB_RVDC32(pipe_stat_reg); in gma_pipe_event_handler()102 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); in gma_pipe_event_handler()103 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; in gma_pipe_event_handler()112 __func__, pipe, PSB_RVDC32(pipe_stat_reg)); in gma_pipe_event_handler()207 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); in gma_irq_handler()240 (void) PSB_RVDC32(PSB_INT_IDENTITY_R); in gma_irq_handler()[all …]
141 dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_enable()144 (void)PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_enable()157 (void)PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_disable()
737 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) macro