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/linux-6.6.21/Documentation/driver-api/phy/
Dphy.rst2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
25 This framework will be of use only to devices that use external PHY (PHY
28 Registering/Unregistering the PHY provider
31 PHY provider refers to an entity that implements one or more PHY instances.
[all …]
/linux-6.6.21/drivers/phy/qualcomm/
DKconfig6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
46 tristate "Qualcomm PCIe Gen2 PHY Driver"
50 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
[all …]
/linux-6.6.21/drivers/phy/broadcom/
DKconfig5 menu "PHY drivers for Broadcom platforms"
8 tristate "BCM63xx USBH PHY driver"
12 Enable this to support the BCM63xx USBH PHY driver.
16 tristate "Broadcom Cygnus PCIe PHY driver"
21 Enable this to support the Broadcom Cygnus PCIe PHY.
25 tristate "Broadcom Stingray USB PHY driver"
30 Enable this to support the Broadcom Stingray USB PHY
36 tristate "Broadcom Kona USB2 PHY Driver"
40 Enable this to support the Broadcom Kona USB 2.0 PHY.
43 tristate "Broadcom Northstar USB 2.0 PHY Driver"
[all …]
/linux-6.6.21/drivers/phy/rockchip/
DKconfig6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
52 tristate "Rockchip Innosilicon MIPI CSI PHY driver"
57 Enable this to support the Rockchip MIPI CSI PHY with
61 tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
[all …]
/linux-6.6.21/drivers/phy/ti/
DKconfig6 tristate "TI DA8xx USB PHY Driver"
11 Enable this to support the USB PHY on DA8xx SoCs.
13 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
16 tristate "TI dm816x USB PHY driver"
33 This option enables support for TI AM654 SerDes PHY used for
53 tristate "OMAP CONTROL PHY Driver"
56 Enable this to add support for the PHY part present in the control
57 module. This driver has API to power on the USB2 PHY and to write to
59 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
60 additional register to power on USB3 PHY/SATA PHY/PCIE PHY
[all …]
/linux-6.6.21/drivers/net/phy/
DKconfig3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
45 for any speed known to the PHY.
55 tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
69 comment "MII PHY device drivers"
[all …]
/linux-6.6.21/drivers/phy/cadence/
DKconfig7 tristate "Cadence Torrent PHY driver"
13 Support for Cadence Torrent PHY.
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
34 tristate "Cadence Sierra PHY Driver"
39 Enable this to support the Cadence Sierra PHY driver
42 tristate "Cadence Salvo PHY Driver"
46 Enable this to support the Cadence SALVO PHY driver,
[all …]
/linux-6.6.21/net/mac80211/
Ddebugfs_sta.c805 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_40MHZ_IN_2G, in link_sta_he_capa_read()
807 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, in link_sta_he_capa_read()
809 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_160MHZ_IN_5G, in link_sta_he_capa_read()
811 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G, in link_sta_he_capa_read()
813 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G, in link_sta_he_capa_read()
815 PFLAG(PHY, 0, CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G, in link_sta_he_capa_read()
833 PFLAG(PHY, 1, DEVICE_CLASS_A, in link_sta_he_capa_read()
835 PFLAG(PHY, 1, LDPC_CODING_IN_PAYLOAD, in link_sta_he_capa_read()
837 PFLAG(PHY, 1, HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US, in link_sta_he_capa_read()
841 PFLAG(PHY, 2, NDP_4x_LTF_AND_3_2US, "NDP-4X-LTF-AND-3-2US"); in link_sta_he_capa_read()
[all …]
/linux-6.6.21/drivers/phy/
DKconfig3 # PHY
6 menu "PHY Subsystem"
9 bool "PHY Core"
11 Generic PHY support.
13 This framework is designed to provide a generic interface for PHY
15 API by which phy drivers can create PHY using the phy framework and
16 phy users can obtain reference to the PHY. All the users of this
23 Generic MIPI D-PHY support.
25 Provides a number of helpers a core functions for MIPI D-PHY
29 tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
[all …]
/linux-6.6.21/drivers/phy/marvell/
DKconfig6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
76 Enable this to support Marvell CP110 UTMI PHY driver.
85 tristate "Marvell USB HSIC 28nm PHY Driver"
89 Enable this to support Marvell USB HSIC PHY driver for Marvell
90 SoC. This driver will do the PHY initialization and shutdown.
[all …]
/linux-6.6.21/drivers/phy/mediatek/
DKconfig6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek T-PHY Driver"
23 Say 'Y' here to add support for MediaTek T-PHY driver,
25 SATA, and meanwhile supports two version T-PHY which have
26 different banks layout, the T-PHY with shared banks between
31 tristate "MediaTek UFS M-PHY driver"
36 Support for UFS M-PHY on MediaTek chipsets.
42 tristate "MediaTek XS-PHY Driver"
[all …]
/linux-6.6.21/drivers/phy/socionext/
DKconfig3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
29 tristate "Uniphier PHY driver for PCIe controller"
35 Enable this to support PHY implemented in PCIe controller
[all …]
/linux-6.6.21/drivers/phy/samsung/
DKconfig6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
37 Enable this to support the Samsung Exynos SoC UFS PHY driver for
39 controller to do PHY related programming.
42 tristate "S5P/Exynos SoC series USB 2.0 PHY driver"
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/phy/
Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device supports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
21 - reg: The PHY port instance number.
22 - #phy-cells: Defined by generic PHY bindings. Must be 0.
[all …]
Dphy-bindings.txt2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY device (used by the PHY subsystem; not to be
[all …]
Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
Dlantiq,vrx200-pcie-phy.yaml7 title: Lantiq VRX200 and ARX300 PCIe PHY
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
27 - description: PHY module clock
37 - description: exclusive PHY reset line
38 - description: shared reset line between the PCIe PHY and PCIe controller
51 description: the offset of the endian registers for this PHY instance in the RCU syscon
55 description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
58 description: Configures the PDI (PHY) registers in big-endian mode
62 description: Configures the PDI (PHY) registers in big-endian mode
Dstarfive,jh7110-pcie-phy.yaml7 title: StarFive JH7110 PCIe 2.0 PHY
27 - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
29 The phandle to System Register Controller syscon node and the PHY connect offset
30 of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
37 - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
38 - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
41 of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
/linux-6.6.21/drivers/phy/hisilicon/
DKconfig6 tristate "hi6220 USB PHY support"
12 Enable this to support the HISILICON HI6220 USB PHY.
17 tristate "hi3660 USB PHY support"
22 Enable this to support the HISILICON HI3660 USB PHY.
27 tristate "hi3670 USB PHY support"
32 Enable this to support the HISILICON HI3670 USB PHY.
37 tristate "hi3670 PCIe PHY support"
42 Enable this to support the HiSilicon hi3670 PCIe PHY.
56 tristate "HiSilicon INNO USB2 PHY support"
61 Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml8 title: TI DP83822 ethernet PHY
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
20 Specifications about the Ethernet PHY can be found at:
33 DP83822 PHY in Fiber mode only.
42 DP83822 PHY only.
43 If present the DP83822 PHY is configured to operate in fiber mode
46 If the fiber mode is not strapped then signal detection for the PHY
48 In fiber mode, auto-negotiation is disabled and the PHY can only work in
53 DP83822 PHY only.
55 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
[all …]
Dethernet-phy.yaml7 title: Ethernet PHY Common Properties
38 If the PHY reports an incorrect ID (or none at all) then the
39 compatible list may contain an entry with the correct PHY ID
57 The ID number for the PHY.
78 Maximum PHY supported speed in Mbits / seconds.
92 If set, indicates the PHY device does not correctly release
99 External clock connected to the PHY. If not specified it is assumed
100 that the PHY uses a fixed crystal or an internal oscillator.
105 If set, indicates the PHY will swap the TX/RX lanes to
112 If set, indicates that PHY will disable swap of the
[all …]
/linux-6.6.21/Documentation/networking/
Dphy.rst2 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
47 mii_id is the address on the bus for the PHY, and regnum is the register
75 between the clock line (RXC or TXC) and the data lines to let the PHY (clock
77 PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
78 the PHY driver and optionally the MAC driver, implement the required delay. The
[all …]
/linux-6.6.21/drivers/phy/freescale/
DKconfig6 tristate "Freescale i.MX8M USB3 PHY"
12 tristate "Mixel LVDS PHY support"
17 Enable this to add support for the Mixel LVDS PHY as found
21 tristate "Mixel MIPI DSI PHY support"
27 Enable this to add support for the Mixel DSI PHY as found
31 tristate "Freescale i.MX8M PCIE PHY"
35 Enable this to add support for the PCIE PHY as found on
41 tristate "Freescale Layerscape Lynx 28G SerDes PHY support"
46 Enable this to add support for the Lynx SerDes 28G PHY as
/linux-6.6.21/drivers/phy/renesas/
DKconfig14 tristate "Renesas R-Car generation 2 USB PHY driver"
18 Support for USB PHY found on Renesas R-Car generation 2 SoCs.
21 tristate "Renesas R-Car generation 3 PCIe PHY driver"
25 Support for the PCIe PHY found on Renesas R-Car generation 3 SoCs.
28 tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
35 Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs.
38 tristate "Renesas R-Car generation 3 USB 3.0 PHY driver"
42 Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
/linux-6.6.21/drivers/phy/starfive/
DKconfig9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
19 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
23 Enable this to support the StarFive PCIe 2.0 PHY,
24 or used as USB 3.0 PHY.
29 tristate "Starfive JH7110 USB 2.0 PHY support"
33 Enable this to support the StarFive USB 2.0 PHY,

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