| /linux-6.6.21/Documentation/devicetree/bindings/clock/ |
| D | samsung,s3c64xx-clock.txt | 74 clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
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| /linux-6.6.21/Documentation/devicetree/bindings/serial/ |
| D | samsung_uart.yaml | 142 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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| /linux-6.6.21/arch/arm/boot/dts/samsung/ |
| D | s3c64xx.dtsi | 123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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| /linux-6.6.21/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 88 #define PCLK_UART0 73 macro
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| D | rk3036-cru.h | 68 #define PCLK_UART0 341 macro
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| D | exynos7-clk.h | 78 #define PCLK_UART0 1 macro
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| D | rk3188-cru-common.h | 84 #define PCLK_UART0 332 macro
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| D | rk3128-cru.h | 108 #define PCLK_UART0 341 macro
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| D | rk3228-cru.h | 107 #define PCLK_UART0 341 macro
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| D | rv1108-cru.h | 116 #define PCLK_UART0 265 macro
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| D | rk3368-cru.h | 125 #define PCLK_UART0 341 macro
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| D | rk3328-cru.h | 141 #define PCLK_UART0 210 macro
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| D | rk3288-cru.h | 133 #define PCLK_UART0 341 macro
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| D | rk3308-cru.h | 176 #define PCLK_UART0 197 macro
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| D | rockchip,rv1126-cru.h | 312 #define PCLK_UART0 250 macro
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| D | rk3399-cru.h | 247 #define PCLK_UART0 352 macro
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| D | rockchip,rk3588-cru.h | 683 #define PCLK_UART0 668 macro
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| D | rk3568-cru.h | 57 #define PCLK_UART0 44 macro
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| /linux-6.6.21/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 244 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
349 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
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| /linux-6.6.21/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 652 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
743 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
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| D | clk-rk3036.c | 417 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
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| D | clk-rk3128.c | 502 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
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| D | clk-rk3228.c | 613 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
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| D | clk-rk3328.c | 783 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
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| /linux-6.6.21/arch/arm/boot/dts/rockchip/ |
| D | rk3xxx.dtsi | 110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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