Searched refs:OTG_H_TIMING_DIV_MODE (Results 1 – 11 of 11) sorted by relevance
| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_optc.c | 102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
180 OTG_H_TIMING_DIV_MODE, h_div); in optc314_set_odm_bypass()
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| D | dcn314_optc.h | 248 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_optc.c | 90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
228 OTG_H_TIMING_DIV_MODE, 0); in optc3_init_odm()
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| D | dcn31_optc.h | 251 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_optc.c | 97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
196 OTG_H_TIMING_DIV_MODE, h_div); in optc32_set_odm_bypass()
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| D | dcn32_optc.h | 176 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_optc.c | 211 OTG_H_TIMING_DIV_MODE, h_div); in optc3_set_odm_bypass()
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
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| D | dcn30_optc.h | 320 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 314 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
319 OTG_H_TIMING_DIV_MODE, h_div); in optc1_program_timing()
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| D | dcn10_optc.h | 544 type OTG_H_TIMING_DIV_MODE;\
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| /linux-6.6.21/drivers/gpu/drm/amd/include/ |
| D | soc21_enum.h | 4314 typedef enum OTG_H_TIMING_DIV_MODE { enum
4319 } OTG_H_TIMING_DIV_MODE; typedef
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