Searched refs:MSI (Results 1 – 25 of 154) sorted by relevance
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| /linux-6.6.21/Documentation/translations/zh_CN/PCI/ |
| D | msi-howto.rst | 16 MSI驱动指南
26 本指南介绍了消息标记中断（MSI）的基本知识，使用MSI相对于传统中断机制的优势，如何
27 改变你的驱动程序以使用MSI或MSI-X，以及在设备不支持MSI时可以尝试的一些基本诊断方法。
30 什么是MSI?
35 MSI能力首次在PCI 2.2中规定，后来在PCI 3.0中得到增强，允许对每个中断进行单独屏蔽。
36 MSI-X功能也随着PCI 3.0被引入。它比MSI支持每个设备更多的中断，并允许独立配置中断。
38 设备可以同时支持MSI和MSI-X，但一次只能启用一个。
41 为什么用MSI?
44 有三个原因可以说明为什么使用MSI比传统的基于针脚的中断有优势。
47 关的中断处理程序，这导致了整个系统性能的降低。MSI从不共享，所以这个问题不会出现。
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| D | pci.rst | 293 中断号码代表从PCI设备到中断控制器的IRQ线。在MSI和MSI-X中（更多内容见下文），中
299 MSI和MSI-X是PCI功能。两者都是“消息信号中断”，通过向本地APIC的DMA写入来向CPU发
300 送中断。MSI和MSI-X的根本区别在于如何分配多个“向量”。MSI需要连续的向量块，而
301 MSI-X可以分配几个单独的向量。
304 的PCI_IRQ_MSI和/或PCI_IRQ_MSIX标志来启用MSI功能。这将导致PCI支持将CPU向量数
305 据编程到PCI设备功能寄存器中。许多架构、芯片组或BIOS不支持MSI或MSI-X，调用
309 对MSI/MSI-X和传统INTx有不同中断处理程序的驱动程序应该在调用
313 使用MSI有（至少）两个真正好的理由：
315 1) 根据定义，MSI是一个排他性的中断向量。这意味着中断处理程序不需要验证其设备是
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
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| D | pciebus-howto.rst | 166 MSI 和 MSI-X 向量资源
169 一旦设备上的MSI或MSI-X中断被启用，它就会一直保持这种模式，直到它们再次被禁用。由于同
171 禁用MSI/MSI-X模式，可能会导致不可预知的行为。
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| /linux-6.6.21/Documentation/PCI/ |
| D | msi-howto.rst | 5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
73 driver has to set up the device to use MSI or MSI-X. Not all machines
80 To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI
86 Using MSI
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| /linux-6.6.21/Documentation/PCI/endpoint/ |
| D | pci-test-howto.rst | 79 to change the vendorid and the number of MSI interrupts used by the function
158 SET IRQ TYPE TO MSI: OKAY
191 SET IRQ TYPE TO MSI-X: OKAY
192 MSI-X1: OKAY
193 MSI-X2: OKAY
194 MSI-X3: OKAY
195 MSI-X4: OKAY
196 MSI-X5: OKAY
197 MSI-X6: OKAY
198 MSI-X7: OKAY
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| D | pci-ntb-function.rst | 115 MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
118 to the MSI/MSI-X address programmed by the host. The ARGUMENT
120 lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
178 in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
179 ring doorbell (MSI-X support will be added later). MSI uses same
180 address for all the interrupts and MSI-X can provide different
181 addresses for different interrupts. The MSI/MSI-X address is provided
182 by the host and the address it gives is based on the MSI/MSI-X
184 using GIC ITS will have the same MSI-X address for all the interrupts.
186 for both MSI and MSI-X, EPF NTB allocates a separate region in the
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| D | pci-test-function.rst | 45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
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| /linux-6.6.21/Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
51 the specific MSI controller.
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| D | msi-controller.yaml | 7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
27 binding of the specific MSI controller.
32 Identifies the node as an MSI controller.
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| D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
6 Layerscape PCIe MSI controller block such as:
12 - msi-controller: indicates that this is a PCIe MSI controller node
21 MSI controller node
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| D | loongson,pch-msi.yaml | 7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
27 to PCH MSI.
35 to PCH MSI.
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| D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
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| D | marvell,odmi-controller.txt | 2 * Marvell ODMI for MSI support
5 which can be used by on-board peripheral for MSI interrupts.
15 - msi-controller : Identifies the node as an MSI controller.
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| /linux-6.6.21/Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
46 | PCH-PIC | | PCH-MSI |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
77 | PCH-PIC | | PCH-MSI |
123 PCH-MSI::
156 - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”；
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| /linux-6.6.21/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
32 - msi-map: Maps a Requester ID to an MSI controller and associated
38 * msi-controller is a single phandle to an MSI controller
52 - msi-parent: Describes the MSI parent of the root complex itself. Where
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
79 * The sideband data provided to the MSI controller is
107 * The sideband data provided to the MSI controller is
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| D | mediatek-pcie-gen3.yaml | 16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
37 | | | | | | | | | | | | (MSI vectors)
40 (MSI SET0) (MSI SET1) ... (MSI SET7)
42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message, and supports 32 MSI vectors
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
46 + PCIe controller node with msi-parent property pointing to MSI node:
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| D | layerscape-pcie-gen4.txt | 17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
23 - msi-parent : See the generic MSI binding described in
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| /linux-6.6.21/Documentation/misc-devices/ |
| D | pci-endpoint-test.rst | 17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
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| D | spear-pcie-gadget.rst | 42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted.
58 INTA, MSI or NO_INT). Select MSI only when you have programmed
60 no_of_msi number of MSI vector needed.
62 send_msi write MSI vector to be sent.
142 if MSI is to be used as interrupt, program no of msi vector needed (say4)::
146 select MSI as interrupt type::
148 # echo MSI >> int_type
165 Should return 4 (number of requested MSI vector)
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| /linux-6.6.21/Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
121 PCH-MSI::
157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
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| /linux-6.6.21/drivers/ntb/ |
| D | Kconfig | 17 bool "MSI Interrupt Support"
20 Support using MSI interrupt forwarding instead of (or in addition to)
21 hardware doorbells. MSI interrupts typically offer lower latency
22 than doorbells and more MSI interrupts can be made available to
24 in the hardware driver for creating the MSI interrupts.
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| /linux-6.6.21/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 1 * Freescale MSI interrupt controller
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
17 region must be added because different MSI group has different MSIIR1 offset.
27 optional, without this, all the MSI interrupts can be used.
29 no splitting an individual MSI register or the associated PIC interrupt).
34 is used for MSI messaging. The address of MSIIR in PCI address space is
35 the MSI message address.
84 Freescale MSI driver calculates the address of MSIIR (in the MSI register
85 block) and sets that address as the MSI message address.
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| /linux-6.6.21/Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3nd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
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| /linux-6.6.21/Documentation/devicetree/bindings/powerpc/4xx/ |
| D | hsta.txt | 10 Currently only the MSI support is used by Linux using the following
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
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