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Searched refs:IS_CHERRYVIEW (Results 1 – 25 of 60) sorted by relevance

123

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dg4x_dp.c53 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; in vlv_get_dpll()
69 } else if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_set_clock()
159 if (IS_CHERRYVIEW(dev_priv)) in intel_dp_prepare()
288 else if (IS_CHERRYVIEW(dev_priv)) in g4x_dp_port_enabled()
470 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
655 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
665 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
668 if (IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
1244 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1309 if (IS_CHERRYVIEW(dev_priv)) { in g4x_dp_init()
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Dintel_pps.c30 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_name()
117 if (IS_CHERRYVIEW(dev_priv)) in vlv_power_sequencer_kick()
129 release_cl_override = IS_CHERRYVIEW(dev_priv) && in vlv_power_sequencer_kick()
348 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_num_pps()
397 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_initial_setup()
487 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
533 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
546 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1515 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1572 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
[all …]
Dintel_pipe_crc.c148 if (!IS_CHERRYVIEW(dev_priv)) in vlv_pipe_crc_ctl_reg()
409 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
539 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
615 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
Di9xx_plane.c140 if (IS_CHERRYVIEW(dev_priv)) in i9xx_plane_has_windowing()
464 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
805 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
839 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
870 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
912 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1016 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
Dintel_lpe_audio.c122 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
Dintel_vga.c20 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
Dintel_sprite_uapi.c63 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_sprite_set_colorkey_ioctl()
Dg4x_hdmi.c55 else if (IS_CHERRYVIEW(dev_priv)) in intel_hdmi_prepare()
729 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
754 if (IS_CHERRYVIEW(dev_priv)) { in g4x_hdmi_init()
Dintel_crtc_state_dump.c352 if (IS_CHERRYVIEW(i915)) in intel_crtc_state_dump()
376 else if (IS_CHERRYVIEW(i915)) in intel_crtc_state_dump()
Dintel_display.c174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
1937 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
1948 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
2057 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
2458 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); in intel_cpu_transcoder_has_m2_n2()
2705 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
2738 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
2916 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
2933 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
2941 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
[all …]
Dintel_sprite.c398 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1343 if (IS_CHERRYVIEW(dev_priv) && in chv_plane_check_rotation()
1560 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_sprite_plane_create()
1569 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1619 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dvlv_dsi_pll.c75 if (IS_CHERRYVIEW(dev_priv)) { in dsi_calc_mnp()
125 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; in vlv_dsi_pclk()
Dintel_hotplug_irq.c140 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
421 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
459 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
474 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
Dintel_dsi_vbt.c497 else if (IS_CHERRYVIEW(dev_priv)) in mipi_exec_gpio()
969 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
1030 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
Dintel_cdclk.c548 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
555 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
2515 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2583 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
3152 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
3221 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
3255 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3393 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3616 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
Dintel_crtc.c347 if (IS_CHERRYVIEW(dev_priv) || in intel_crtc_init()
491 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
/linux-6.6.21/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c175 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
287 !IS_CHERRYVIEW(gt->i915)) in live_forcewake_domains()
/linux-6.6.21/drivers/gpu/drm/i915/gt/
Dintel_gtt.c32 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); in intel_vm_no_concurrent_access_wa()
418 else if (IS_CHERRYVIEW(i915)) in gtt_write_workarounds()
657 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) in setup_private_pat()
Dintel_rc6.c619 if (IS_CHERRYVIEW(i915)) in intel_rc6_init()
657 if (IS_CHERRYVIEW(i915)) in intel_rc6_enable()
817 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
Dintel_rps.c842 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1544 else if (IS_CHERRYVIEW(i915)) in intel_rps_enable()
1644 else if (IS_CHERRYVIEW(i915)) in intel_gpu_freq()
1661 else if (IS_CHERRYVIEW(i915)) in intel_freq_opcode()
1848 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; in rps_work()
1864 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; in rps_work()
1992 if (IS_CHERRYVIEW(i915)) in intel_rps_init()
2081 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2110 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in __read_cagf()
Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
Dintel_gt_pm_debugfs.c324 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
355 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
/linux-6.6.21/drivers/gpu/drm/i915/soc/
Dintel_gmch.c85 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()
/linux-6.6.21/drivers/gpu/drm/i915/
Dvlv_suspend.c386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
431 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
Dvlv_sideband.c224 if (IS_CHERRYVIEW(i915)) in vlv_dpio_phy_iosf_port()

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