1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 4 */ 5 #ifndef _IOAT_REGISTERS_H_ 6 #define _IOAT_REGISTERS_H_ 7 8 #define IOAT_PCI_DMACTRL_OFFSET 0x48 9 #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 10 #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 11 12 #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 13 #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 14 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 15 #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 16 17 /* MMIO Device Registers */ 18 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 19 20 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 21 #define IOAT_XFERCAP_4KB 12 22 #define IOAT_XFERCAP_8KB 13 23 #define IOAT_XFERCAP_16KB 14 24 #define IOAT_XFERCAP_32KB 15 25 #define IOAT_XFERCAP_32GB 0 26 27 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 28 #define IOAT_GENCTRL_DEBUG_EN 0x01 29 30 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 31 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 32 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 33 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 34 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 35 36 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 37 38 #define IOAT_VER_OFFSET 0x08 /* 8-bit */ 39 #define IOAT_VER_MAJOR_MASK 0xF0 40 #define IOAT_VER_MINOR_MASK 0x0F 41 #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 42 #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 43 44 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 45 46 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 47 #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 48 #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 49 50 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 51 #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 52 #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 53 #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 54 #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 55 56 #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 57 #define IOAT_CAP_PAGE_BREAK 0x00000001 58 #define IOAT_CAP_CRC 0x00000002 59 #define IOAT_CAP_SKIP_MARKER 0x00000004 60 #define IOAT_CAP_DCA 0x00000010 61 #define IOAT_CAP_CRC_MOVE 0x00000020 62 #define IOAT_CAP_FILL_BLOCK 0x00000040 63 #define IOAT_CAP_APIC 0x00000080 64 #define IOAT_CAP_XOR 0x00000100 65 #define IOAT_CAP_PQ 0x00000200 66 #define IOAT_CAP_DWBES 0x00002000 67 #define IOAT_CAP_RAID16SS 0x00020000 68 #define IOAT_CAP_DPS 0x00800000 69 70 #define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ 71 72 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 73 74 /* DMA Channel Registers */ 75 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 76 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 77 #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 78 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 79 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 80 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 81 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 82 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 83 #define IOAT_CHANCTRL_INT_REARM 0x0001 84 #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 85 IOAT_CHANCTRL_ERR_INT_EN |\ 86 IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 87 IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 88 89 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 90 #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 91 #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 92 93 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 94 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 95 #define IOAT_CHANSTS_SOFT_ERR 0x10ULL 96 #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 97 #define IOAT_CHANSTS_STATUS 0x7ULL 98 #define IOAT_CHANSTS_ACTIVE 0x0 99 #define IOAT_CHANSTS_DONE 0x1 100 #define IOAT_CHANSTS_SUSPENDED 0x2 101 #define IOAT_CHANSTS_HALTED 0x3 102 103 104 105 #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 106 107 #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 108 #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 109 #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 110 111 /* CB DCA Memory Space Registers */ 112 #define IOAT_DCAOFFSET_OFFSET 0x14 113 /* CB_BAR + IOAT_DCAOFFSET value */ 114 #define IOAT_DCA_VER_OFFSET 0x00 115 #define IOAT_DCA_VER_MAJOR_MASK 0xF0 116 #define IOAT_DCA_VER_MINOR_MASK 0x0F 117 118 #define IOAT_DCA_COMP_OFFSET 0x02 119 #define IOAT_DCA_COMP_V1 0x1 120 121 #define IOAT_FSB_CAPABILITY_OFFSET 0x04 122 #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 123 124 #define IOAT_PCI_CAPABILITY_OFFSET 0x06 125 #define IOAT_PCI_CAPABILITY_MEMWR 0x1 126 127 #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 128 #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 129 130 #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 131 #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 132 133 #define IOAT_APICID_TAG_MAP_OFFSET 0x0C 134 #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 135 #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 136 #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 137 #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 138 #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 139 #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 140 #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 141 #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 142 #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 143 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 144 #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 145 146 #define IOAT_DCA_GREQID_OFFSET 0x10 147 #define IOAT_DCA_GREQID_SIZE 0x04 148 #define IOAT_DCA_GREQID_MASK 0xFFFF 149 #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 150 #define IOAT_DCA_GREQID_VALID 0x20000000 151 #define IOAT_DCA_GREQID_LASTID 0x80000000 152 153 #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 154 #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 155 156 #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 157 #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 158 159 #define IOAT3_CSI_CONTROL_OFFSET 0x0C 160 #define IOAT3_CSI_CONTROL_PREFETCH 0x1 161 162 #define IOAT3_PCI_CONTROL_OFFSET 0x0E 163 #define IOAT3_PCI_CONTROL_MEMWR 0x1 164 165 #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 166 #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 167 #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 168 169 #define IOAT3_DCA_GREQID_OFFSET 0x02 170 171 #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 172 #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 173 #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 174 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 175 #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 176 #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 177 #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 178 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 179 #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 180 #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 181 #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 182 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 183 184 #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 185 #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 186 #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 187 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 188 #define IOAT_CHANCMD_RESET 0x20 189 #define IOAT_CHANCMD_RESUME 0x10 190 #define IOAT_CHANCMD_ABORT 0x08 191 #define IOAT_CHANCMD_SUSPEND 0x04 192 #define IOAT_CHANCMD_APPEND 0x02 193 #define IOAT_CHANCMD_START 0x01 194 195 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 196 #define IOAT_CHANCMP_OFFSET_LOW 0x18 197 #define IOAT_CHANCMP_OFFSET_HIGH 0x1C 198 199 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 200 #define IOAT_CDAR_OFFSET_LOW 0x20 201 #define IOAT_CDAR_OFFSET_HIGH 0x24 202 203 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 204 #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 205 #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 206 #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 207 #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 208 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 209 #define IOAT_CHANERR_CHANCMD_ERR 0x0020 210 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 211 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 212 #define IOAT_CHANERR_READ_DATA_ERR 0x0100 213 #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 214 #define IOAT_CHANERR_CONTROL_ERR 0x0400 215 #define IOAT_CHANERR_LENGTH_ERR 0x0800 216 #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 217 #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 218 #define IOAT_CHANERR_SOFT_ERR 0x4000 219 #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 220 #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 221 #define IOAT_CHANERR_XOR_Q_ERR 0x20000 222 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 223 224 #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 225 #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \ 226 IOAT_CHANERR_WRITE_DATA_ERR) 227 228 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 229 230 #define IOAT_CHAN_DRSCTL_OFFSET 0xB6 231 #define IOAT_CHAN_DRSZ_4KB 0x0000 232 #define IOAT_CHAN_DRSZ_8KB 0x0001 233 #define IOAT_CHAN_DRSZ_2MB 0x0009 234 #define IOAT_CHAN_DRS_EN 0x0100 235 #define IOAT_CHAN_DRS_AUTOWRAP 0x0200 236 237 #define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC 238 #define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 239 #define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 240 241 #define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 242 #define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ 243 #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ 244 #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ 245 246 #define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 247 #define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ 248 #define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ 249 #define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ 250 251 #endif /* _IOAT_REGISTERS_H_ */ 252