Searched refs:INTEL_CX0_BOTH_LANES (Results 1 – 1 of 1) sorted by relevance
| /linux-6.6.21/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 30 #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0) macro
42 if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) || in lane_mask_to_lane()
374 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
376 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
380 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1), in intel_cx0_phy_set_signal_levels()
408 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD, in intel_cx0_phy_set_signal_levels()
413 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
1843 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1848 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, in intel_c10_pll_program()
1851 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
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