Searched refs:IMX5_CLK_LDB_DI0_GATE (Results 1 – 4 of 4) sorted by relevance
131 #define IMX5_CLK_LDB_DI0_GATE 123 macro
88 <&clks IMX5_CLK_LDB_DI0_GATE>,
513 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); in mx53_clocks_init()
481 <&clks IMX5_CLK_LDB_DI0_GATE>,