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/linux-6.6.21/arch/powerpc/crypto/
Dghashp10-ppc.pl57 my ($zero,$t0,$t1,$t2,$xC2,$H,$Hh,$Hl,$lemask)=map("v$_",(4..12));
60 my ($t4,$t5,$t6) = ($Hl,$H,$Hh);
74 lvx_u $H,0,r4 # load H
80 le?vperm $H,$H,$H,5
92 vspltb $t1,$H,0 # most significant byte
93 vsl $H,$H,$t0 # H<<=1
96 vxor $H,$H,$t1 # twisted H
98 vsldoi $H,$H,$H,8 # twist even more ...
100 vsldoi $Hl,$zero,$H,8 # ... and split
101 vsldoi $Hh,$H,$zero,8
[all …]
Daes-gcm-p10.S14 # X1 * H^4 + X2 * H^3 + x3 * H^2 + X4 * H =
18 # (X4.h * H.h + X4.l * H.l + X4 * H)
21 # H Poly = v2
23 # ( H.l, H, H.h)
24 # ( H^2.l, H^2, H^2.h)
25 # ( H^3.l, H^3, H^3.h)
26 # ( H^4.l, H^4, H^4.h)
247 vpmsumd 24, 13, 15 # H4.L * X.H + H4.H * X.L
248 vpmsumd 25, 10, 16 # H3.L * X1.H + H3.H * X1.L
256 # sum hash and reduction with H Poly
[all …]
/linux-6.6.21/drivers/crypto/vmx/
Dghashp8-ppc.pl57 my ($zero,$t0,$t1,$t2,$xC2,$H,$Hh,$Hl,$lemask)=map("v$_",(4..12));
72 lvx_u $H,0,r4 # load H
78 le?vperm $H,$H,$H,5
90 vspltb $t1,$H,0 # most significant byte
91 vsl $H,$H,$t0 # H<<=1
94 vxor $H,$H,$t1 # twisted H
96 vsldoi $H,$H,$H,8 # twist even more ...
98 vsldoi $Hl,$zero,$H,8 # ... and split
99 vsldoi $Hh,$H,$zero,8
103 stvx_u $H, r9,r3
[all …]
/linux-6.6.21/Documentation/staging/
Dlzo.rst142 Always followed by exactly one byte : H H H H H H H H
143 distance = (H << 2) + D + 1
152 Always followed by exactly one byte : H H H H H H H H
153 distance = (H << 2) + D + 2049
155 0 0 0 1 H L L L (16..31)
159 distance = 16384 + (H << 14) + D
168 zeros if distance = 0xbfff, i.e. H = 1 and the D bits are all 1.
183 Always followed by exactly one byte : H H H H H H H H
184 distance = (H << 3) + D + 1
190 Always followed by exactly one byte : H H H H H H H H
[all …]
/linux-6.6.21/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
158 # D: 29.500 MHz, H: 29.738 kHz, V: 60.00 Hz
179 # D: 32.668 MHz, H: 35.820 kHz, V: 60.00 Hz
200 # D: 40.00 MHz, H: 37.879 kHz, V: 60.32 Hz
[all …]
/linux-6.6.21/Documentation/driver-api/media/drivers/ccs/
Dmk-ccs-regs51 open(my $H, "> $header") or die "can't open $header";
81 for my $fh ($H, $LH) {
93 print $H <<EOF
100 print $H "#include <linux/bits.h>\n\n" if defined $kernel;
102 print $H <<EOF
107 print $H "#define CCS_FL_16BIT " . bit_def("CCS_FL_BASE") . "\n";
108 print $H "#define CCS_FL_32BIT " . bit_def("CCS_FL_BASE + 1") . "\n";
109 print $H "#define CCS_FL_FLOAT_IREAL " . bit_def("CCS_FL_BASE + 2") . "\n";
110 print $H "#define CCS_FL_IREAL " . bit_def("CCS_FL_BASE + 3") . "\n";
112 print $H <<EOF
[all …]
/linux-6.6.21/drivers/pinctrl/sunxi/
Dpinctrl-sun6i-a31.c827 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 0), PINCTRL_SUN6I_A31,
831 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 1), PINCTRL_SUN6I_A31,
835 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 2), PINCTRL_SUN6I_A31,
839 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 3), PINCTRL_SUN6I_A31,
843 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 4), PINCTRL_SUN6I_A31,
847 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 5), PINCTRL_SUN6I_A31,
851 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 6), PINCTRL_SUN6I_A31,
855 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 7), PINCTRL_SUN6I_A31,
859 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 8), PINCTRL_SUN6I_A31,
863 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
Dpinctrl-sun50i-a100.c533 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
551 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
565 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
588 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
596 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
Dpinctrl-sun9i-a80.c618 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
622 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
626 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
630 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
634 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
638 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
642 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
648 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
658 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
[all …]
Dpinctrl-sun4i-a10.c815 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
824 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
833 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
842 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
851 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
860 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
869 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
881 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
893 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
908 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
Dpinctrl-sun8i-a83t.c514 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
Dpinctrl-sun50i-a64.c515 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
525 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
530 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
560 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
Dpinctrl-sun50i-h616.c302 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
324 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
353 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
361 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
369 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
[all …]
/linux-6.6.21/arch/arm/boot/dts/st/
Dstm32mp15-pinctrl.dtsi93 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
96 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
97 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
98 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
99 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
100 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
105 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
107 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
114 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
117 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
[all …]
Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts94 <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
95 <STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */
104 <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */
105 <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */
106 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
107 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
108 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
109 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
110 <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */
111 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
/linux-6.6.21/Documentation/ABI/testing/
Dsysfs-class-pwm4 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
13 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
22 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
29 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
37 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
44 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
53 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
60 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
67 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
75 Contact: H Hartley Sweeten <hsweeten@visionengravers.com>
/linux-6.6.21/drivers/media/pci/solo6x10/
DKconfig3 tristate "Bluecherry / Softlogic 6x10 capture cards (MPEG-4/H.264)"
13 This driver supports the Bluecherry H.264 and MPEG-4 hardware
17 * Bluecherry BC-H16480A (PCIe, 16 port, H.264)
18 * Bluecherry BC-H04120A (PCIe, 4 port, H.264)
19 * Bluecherry BC-H04120A-MPCI (Mini-PCI, 4 port, H.264)
/linux-6.6.21/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S71 movzx b ## H, %edi;\
74 movzx a ## H, %edi;\
81 movzx b ## H, %edi;\
84 movzx a ## H, %edi;\
109 movzx b ## H, %edi;\
112 movzx a ## H, %edi;\
120 movzx b ## H, %edi;\
122 movzx a ## H, %edi;\
144 movzx a ## H, %edi;\
147 movzx b ## H, %edi;\
[all …]
Dtwofish-i586-asm_32.S73 movzx b ## H, %edi;\
76 movzx a ## H, %edi;\
83 movzx b ## H, %edi;\
86 movzx a ## H, %edi;\
111 movzx b ## H, %edi;\
114 movzx a ## H, %edi;\
121 movzx b ## H, %edi;\
124 movzx a ## H, %edi;\
148 movzx a ## H, %edi;\
151 movzx b ## H, %edi;\
[all …]
/linux-6.6.21/drivers/gpu/drm/sprd/
Dmegacores_pll.c16 #define H 1 macro
237 range[H] = INFINITY; in dphy_timing_config()
244 range[H] = 95 * scale; in dphy_timing_config()
245 tmp = AVERAGE(range[L], range[H]); in dphy_timing_config()
246 val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1; in dphy_timing_config()
248 range[H] = 85 * scale + 6 * t_ui; in dphy_timing_config()
249 tmp |= AVERAGE(range[L], range[H]) << 16; in dphy_timing_config()
250 val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1; in dphy_timing_config()
255 range[H] = INFINITY; in dphy_timing_config()
266 range[H] = INFINITY; in dphy_timing_config()
[all …]
/linux-6.6.21/drivers/gpu/drm/i915/gt/shaders/clear_kernel/
Dhsw.asm97 mov(16) g3<1>UD 0x00000000UD { align1 1H };
98 mov(16) g4<1>UD 0x00000000UD { align1 1H };
99 mov(16) g5<1>UD 0x00000000UD { align1 1H };
100 mov(16) g6<1>UD 0x00000000UD { align1 1H };
101 mov(16) g7<1>UD 0x00000000UD { align1 1H };
102 mov(16) g8<1>UD 0x00000000UD { align1 1H };
103 mov(16) g9<1>UD 0x00000000UD { align1 1H };
104 mov(16) g10<1>UD 0x00000000UD { align1 1H };
113 mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
Divb.asm95 mov(16) g3<1>UD 0x00000000UD { align1 1H };
96 mov(16) g4<1>UD 0x00000000UD { align1 1H };
97 mov(16) g5<1>UD 0x00000000UD { align1 1H };
98 mov(16) g6<1>UD 0x00000000UD { align1 1H };
99 mov(16) g7<1>UD 0x00000000UD { align1 1H };
100 mov(16) g8<1>UD 0x00000000UD { align1 1H };
101 mov(16) g9<1>UD 0x00000000UD { align1 1H };
102 mov(16) g10<1>UD 0x00000000UD { align1 1H };
111 mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
/linux-6.6.21/arch/arm/crypto/
Dsha256-armv4.pl61 $H="r11";
62 @V=($A,$B,$C,$D,$E,$F,$G,$H);
230 ldmia $ctx,{$A,$B,$C,$D,$E,$F,$G,$H}
270 add $H,$H,$t1
271 stmia $t3,{$A,$B,$C,$D,$E,$F,$G,$H}
472 sub $H,sp,#16*4+16
475 bic $H,$H,#15 @ align for 128-bit stores
477 mov sp,$H @ alloca
506 ldmia $ctx,{$A-$H}
564 add $H,$H,$t4
[all …]
/linux-6.6.21/fs/ext4/
Dhash.c36 #define H(x, y, z) ((x) ^ (y) ^ (z)) macro
78 ROUND(H, a, b, c, d, in[3] + K3, 3); in half_md4_transform()
79 ROUND(H, d, a, b, c, in[7] + K3, 9); in half_md4_transform()
80 ROUND(H, c, d, a, b, in[2] + K3, 11); in half_md4_transform()
81 ROUND(H, b, c, d, a, in[6] + K3, 15); in half_md4_transform()
82 ROUND(H, a, b, c, d, in[1] + K3, 3); in half_md4_transform()
83 ROUND(H, d, a, b, c, in[5] + K3, 9); in half_md4_transform()
84 ROUND(H, c, d, a, b, in[0] + K3, 11); in half_md4_transform()
85 ROUND(H, b, c, d, a, in[4] + K3, 15); in half_md4_transform()
100 #undef H
/linux-6.6.21/drivers/scsi/arm/
Dcumana_1.c42 #define H(v) (((v)>>16)|((v) & 0xffff0000)) macro
64 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
65 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
66 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
67 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
68 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
69 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
70 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
71 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()

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