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Searched refs:GICD_CTLR (Results 1 – 5 of 5) sorted by relevance

/linux-6.6.21/tools/testing/selftests/kvm/lib/aarch64/
Dgic_v3.c38 while (readl(gicv3_data.dist_base + GICD_CTLR) & GICD_CTLR_RWP) { in gicv3_gicd_wait_for_rwp()
334 writel(0, dist_base + GICD_CTLR); in gicv3_dist_init()
357 GICD_CTLR_ENABLE_G1, dist_base + GICD_CTLR); in gicv3_dist_init()
/linux-6.6.21/tools/testing/selftests/kvm/include/aarch64/
Dgic_v3.h14 #define GICD_CTLR 0x0000 macro
/linux-6.6.21/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c71 case GICD_CTLR: in vgic_mmio_read_v3_misc()
111 case GICD_CTLR: { in vgic_mmio_write_v3_misc()
179 case GICD_CTLR: in vgic_mmio_uaccess_write_v3_misc()
620 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
/linux-6.6.21/include/linux/irqchip/
Darm-gic-v3.h13 #define GICD_CTLR 0x0000 macro
114 #define GICR_CTLR GICD_CTLR
/linux-6.6.21/drivers/irqchip/
Dirq-gic-v3.c250 while (readl_relaxed(base + GICD_CTLR) & bit) { in gic_do_wait_for_rwp()
915 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init()
952 writel_relaxed(val, base + GICD_CTLR); in gic_dist_init()
1125 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; in gic_dist_security_disabled()