/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ |
D | gfxhub_v1_2.c | 39 return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24; in gfxhub_v1_2_get_mc_fb_offset() 52 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs() 57 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_setup_vm_pt_regs() 92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 109 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() 113 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs() [all …]
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D | gfx_v9_4_3.c | 198 dev_inst = GET_INST(GC, i); in gfx_v9_4_3_init_golden_registers() 257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring() 344 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); in gfx_v9_4_3_get_gpu_clock_counter() 345 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v9_4_3_get_gpu_clock_counter() 346 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v9_4_3_get_gpu_clock_counter() 547 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh() 552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind() 557 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_ind() 564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs() 572 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); in wave_read_regs() [all …]
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D | amdgpu_amdkfd_gfx_v9.c | 54 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); in kgd_gfx_v9_lock_srbm() 59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm() 94 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings() 95 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings() 171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts() 238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load() 241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load() 248 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL), in kgd_gfx_v9_hqd_load() 278 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load() 280 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load() [all …]
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D | amdgpu_amdkfd_gc_9_4_3.c | 48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset() 228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping() 299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load() 300 hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI); in kgd_gfx_v9_4_3_hqd_load() 309 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL), in kgd_gfx_v9_4_3_hqd_load() 339 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_4_3_hqd_load() 341 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_4_3_hqd_load() 343 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_4_3_hqd_load() 345 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_hqd_load() 348 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1), in kgd_gfx_v9_4_3_hqd_load() [all …]
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D | jpeg_v4_0_3.c | 108 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_sw_init() 201 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start_sriov() 317 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_hw_init() 332 VCN, GET_INST(VCN, i), in jpeg_v4_0_3_hw_init() 418 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating() 443 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating() 476 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start() 563 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_stop() 601 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, in jpeg_v4_0_3_dec_ring_get_rptr() 620 JPEG, GET_INST(JPEG, ring->me), in jpeg_v4_0_3_dec_ring_get_wptr() [all …]
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D | vcn_v4_0_3.c | 112 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_sw_init() 224 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_hw_init() 235 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init() 243 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init() 338 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume() 526 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_disable_clock_gating() 670 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_enable_clock_gating() 722 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_start_dpg_mode() 883 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start_sriov() 1058 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start() [all …]
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D | amdgpu_vcn.h | 147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \ 150 VCN, GET_INST(VCN, inst_idx), \
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D | sdma_v4_4_2.c | 62 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset() 1798 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state() 1803 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state() 1901 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs() 2133 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_query_ras_error_count() 2164 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_reset_ras_error_count()
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D | soc15_common.h | 28 #define GET_INST(ip, inst) \ macro
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D | nbio_v7_9.c | 85 dev_inst = GET_INST(SDMA0, instance); in nbio_v7_9_sdma_doorbell_range()
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/linux-6.6.21/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
D | smu_v13_0_6_ppt.c | 695 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data() 1967 xcc0 = GET_INST(GC, 0); in smu_v13_0_6_get_gpu_metrics()
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/linux-6.6.21/drivers/gpu/drm/amd/amdkfd/ |
D | kfd_device.c | 620 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()
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