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Searched refs:GENENB__BLK_IO_BASE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7072 #define GENENB__BLK_IO_BASE__SHIFT 0x00000000 macro
Ddce_8_0_sh_mask.h10632 #define GENENB__BLK_IO_BASE__SHIFT 0x0 macro
Ddce_10_0_sh_mask.h11016 #define GENENB__BLK_IO_BASE__SHIFT 0x0 macro
Ddce_11_0_sh_mask.h10828 #define GENENB__BLK_IO_BASE__SHIFT 0x0 macro
Ddce_11_2_sh_mask.h12082 #define GENENB__BLK_IO_BASE__SHIFT 0x0 macro
Ddce_12_0_sh_mask.h2221 #define GENENB__BLK_IO_BASE__SHIFT … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h258 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_2_1_sh_mask.h4456 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_1_0_sh_mask.h860 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_1_5_sh_mask.h5161 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_0_2_sh_mask.h271 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_1_6_sh_mask.h368 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_2_0_0_sh_mask.h271 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_0_0_sh_mask.h252 #define GENENB__BLK_IO_BASE__SHIFT … macro
Ddcn_3_2_0_sh_mask.h4455 #define GENENB__BLK_IO_BASE__SHIFT … macro