1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11 #ifndef __SOF_INTEL_HDA_H
12 #define __SOF_INTEL_HDA_H
13
14 #include <linux/soundwire/sdw.h>
15 #include <linux/soundwire/sdw_intel.h>
16 #include <sound/compress_driver.h>
17 #include <sound/hda_codec.h>
18 #include <sound/hdaudio_ext.h>
19 #include "../sof-client-probes.h"
20 #include "../sof-audio.h"
21 #include "shim.h"
22
23 /* PCI registers */
24 #define PCI_TCSEL 0x44
25 #define PCI_PGCTL PCI_TCSEL
26 #define PCI_CGCTL 0x48
27
28 /* PCI_PGCTL bits */
29 #define PCI_PGCTL_ADSPPGD BIT(2)
30 #define PCI_PGCTL_LSRMD_MASK BIT(4)
31
32 /* PCI_CGCTL bits */
33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
34 #define PCI_CGCTL_ADSPDCGE BIT(1)
35
36 /* Legacy HDA registers and bits used - widths are variable */
37 #define SOF_HDA_GCAP 0x0
38 #define SOF_HDA_GCTL 0x8
39 /* accept unsol. response enable */
40 #define SOF_HDA_GCTL_UNSOL BIT(8)
41 #define SOF_HDA_LLCH 0x14
42 #define SOF_HDA_INTCTL 0x20
43 #define SOF_HDA_INTSTS 0x24
44 #define SOF_HDA_WAKESTS 0x0E
45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
46 #define SOF_HDA_RIRBSTS 0x5d
47
48 /* SOF_HDA_GCTL register bist */
49 #define SOF_HDA_GCTL_RESET BIT(0)
50
51 /* SOF_HDA_INCTL regs */
52 #define SOF_HDA_INT_GLOBAL_EN BIT(31)
53 #define SOF_HDA_INT_CTRL_EN BIT(30)
54 #define SOF_HDA_INT_ALL_STREAM 0xff
55
56 /* SOF_HDA_INTSTS regs */
57 #define SOF_HDA_INTSTS_GIS BIT(31)
58
59 #define SOF_HDA_MAX_CAPS 10
60 #define SOF_HDA_CAP_ID_OFF 16
61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
62 SOF_HDA_CAP_ID_OFF)
63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
64
65 #define SOF_HDA_GTS_CAP_ID 0x1
66 #define SOF_HDA_ML_CAP_ID 0x2
67
68 #define SOF_HDA_PP_CAP_ID 0x3
69 #define SOF_HDA_REG_PP_PPCH 0x10
70 #define SOF_HDA_REG_PP_PPCTL 0x04
71 #define SOF_HDA_REG_PP_PPSTS 0x08
72 #define SOF_HDA_PPCTL_PIE BIT(31)
73 #define SOF_HDA_PPCTL_GPROCEN BIT(30)
74
75 /*Vendor Specific Registers*/
76 #define SOF_HDA_VS_D0I3C 0x104A
77
78 /* D0I3C Register fields */
79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
81
82 /* DPIB entry size: 8 Bytes = 2 DWords */
83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
84
85 #define SOF_HDA_SPIB_CAP_ID 0x4
86 #define SOF_HDA_DRSM_CAP_ID 0x5
87
88 #define SOF_HDA_SPIB_BASE 0x08
89 #define SOF_HDA_SPIB_INTERVAL 0x08
90 #define SOF_HDA_SPIB_SPIB 0x00
91 #define SOF_HDA_SPIB_MAXFIFO 0x04
92
93 #define SOF_HDA_PPHC_BASE 0x10
94 #define SOF_HDA_PPHC_INTERVAL 0x10
95
96 #define SOF_HDA_PPLC_BASE 0x10
97 #define SOF_HDA_PPLC_MULTI 0x10
98 #define SOF_HDA_PPLC_INTERVAL 0x10
99
100 #define SOF_HDA_DRSM_BASE 0x08
101 #define SOF_HDA_DRSM_INTERVAL 0x08
102
103 /* Descriptor error interrupt */
104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
105
106 /* FIFO error interrupt */
107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
108
109 /* Buffer completion interrupt */
110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
111
112 #define SOF_HDA_CL_DMA_SD_INT_MASK \
113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
115 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
117
118 /* Intel HD Audio Code Loader DMA Registers */
119 #define SOF_HDA_ADSP_LOADER_BASE 0x80
120 #define SOF_HDA_ADSP_DPLBASE 0x70
121 #define SOF_HDA_ADSP_DPUBASE 0x74
122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
123
124 /* Stream Registers */
125 #define SOF_HDA_ADSP_REG_SD_CTL 0x00
126 #define SOF_HDA_ADSP_REG_SD_STS 0x03
127 #define SOF_HDA_ADSP_REG_SD_LPIB 0x04
128 #define SOF_HDA_ADSP_REG_SD_CBL 0x08
129 #define SOF_HDA_ADSP_REG_SD_LVI 0x0C
130 #define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
131 #define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
132 #define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
133 #define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
134 #define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
135 #define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
137
138 /* CL: Software Position Based FIFO Capability Registers */
139 #define SOF_DSP_REG_CL_SPBFIFO \
140 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
145
146 /* Stream Number */
147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
151
152 #define HDA_DSP_HDA_BAR 0
153 #define HDA_DSP_PP_BAR 1
154 #define HDA_DSP_SPIB_BAR 2
155 #define HDA_DSP_DRSM_BAR 3
156 #define HDA_DSP_BAR 4
157
158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
159
160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
161
162 #define HDA_DSP_PANIC_OFFSET(x) \
163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
164
165 /* SRAM window 0 FW "registers" */
166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
168 /* FW and ROM share offset 4 */
169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
172
173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
174
175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300
176 /*
177 * Timeout in us, for setting the stream RUN bit, during
178 * start/stop the stream. The timeout expires if new RUN bit
179 * value cannot be read back within the specified time.
180 */
181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300
182
183 #define HDA_DSP_SPIB_ENABLE 1
184 #define HDA_DSP_SPIB_DISABLE 0
185
186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
187
188 #define HDA_DSP_STACK_DUMP_SIZE 32
189
190 /* ROM/FW status register */
191 #define FSR_STATE_MASK GENMASK(23, 0)
192 #define FSR_WAIT_STATE_MASK GENMASK(27, 24)
193 #define FSR_MODULE_MASK GENMASK(30, 28)
194 #define FSR_HALTED BIT(31)
195 #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK)
196 #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24)
197 #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28)
198
199 /* Wait states */
200 #define FSR_WAIT_FOR_IPC_BUSY 0x1
201 #define FSR_WAIT_FOR_IPC_DONE 0x2
202 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
203 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
204 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
205 #define FSR_WAIT_FOR_CSE_CSR 0x6
206
207 /* Module codes */
208 #define FSR_MOD_ROM 0x0
209 #define FSR_MOD_ROM_BYP 0x1
210 #define FSR_MOD_BASE_FW 0x2
211 #define FSR_MOD_LP_BOOT 0x3
212 #define FSR_MOD_BRNGUP 0x4
213 #define FSR_MOD_ROM_EXT 0x5
214
215 /* State codes (module dependent) */
216 /* Module independent states */
217 #define FSR_STATE_INIT 0x0
218 #define FSR_STATE_INIT_DONE 0x1
219 #define FSR_STATE_FW_ENTERED 0x5
220
221 /* ROM states */
222 #define FSR_STATE_ROM_INIT FSR_STATE_INIT
223 #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE
224 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
225 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
226 #define FSR_STATE_ROM_FW_FW_LOADED 0x4
227 #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED
228 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
229 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
230 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
231 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
232 #define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
233
234 /* (ROM) CSE states */
235 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
236 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
237 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
238 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
239
240 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
241 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
242 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
243 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
244 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
245
246 /* BRINGUP (or BRNGUP) states */
247 #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT
248 #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE
249 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
250 #define FSR_STATE_BRINGUP_UNPACK_START 0X3
251 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
252 #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED
253
254 /* ROM status/error values */
255 #define HDA_DSP_ROM_CSE_ERROR 40
256 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
257 #define HDA_DSP_ROM_IMR_TO_SMALL 42
258 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
259 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
260 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
261 #define HDA_DSP_ROM_L2_CACHE_ERROR 46
262 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
263 #define HDA_DSP_ROM_API_PTR_INVALID 50
264 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
265 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
266 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
267 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
268 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
269 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
270 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
271
272 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000
273 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
274
275 /* various timeout values */
276 #define HDA_DSP_PU_TIMEOUT 50
277 #define HDA_DSP_PD_TIMEOUT 50
278 #define HDA_DSP_RESET_TIMEOUT_US 50000
279 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
280 #define HDA_DSP_INIT_TIMEOUT_US 500000
281 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
282 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
283 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
284 #define HDA_DSP_REG_POLL_RETRY_COUNT 50
285
286 #define HDA_DSP_ADSPIC_IPC BIT(0)
287 #define HDA_DSP_ADSPIS_IPC BIT(0)
288
289 /* Intel HD Audio General DSP Registers */
290 #define HDA_DSP_GEN_BASE 0x0
291 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
292 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
293 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
294 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
295 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
296
297 #define HDA_DSP_REG_ADSPIC2_SNDW BIT(5)
298 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
299
300 /* Intel HD Audio Inter-Processor Communication Registers */
301 #define HDA_DSP_IPC_BASE 0x40
302 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
303 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
304 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
305 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
306 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
307
308 /* Intel Vendor Specific Registers */
309 #define HDA_VS_INTEL_EM2 0x1030
310 #define HDA_VS_INTEL_EM2_L1SEN BIT(13)
311 #define HDA_VS_INTEL_LTRP 0x1048
312 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
313
314 /* HIPCI */
315 #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
316 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
317
318 /* HIPCIE */
319 #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
320 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
321
322 /* HIPCCTL */
323 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
324 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
325
326 /* HIPCT */
327 #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
328 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
329
330 /* HIPCTE */
331 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
332
333 #define HDA_DSP_ADSPIC_CL_DMA BIT(1)
334 #define HDA_DSP_ADSPIS_CL_DMA BIT(1)
335
336 /* Delay before scheduling D0i3 entry */
337 #define BXT_D0I3_DELAY 5000
338
339 #define FW_CL_STREAM_NUMBER 0x1
340 #define HDA_FW_BOOT_ATTEMPTS 3
341
342 /* ADSPCS - Audio DSP Control & Status */
343
344 /*
345 * Core Reset - asserted high
346 * CRST Mask for a given core mask pattern, cm
347 */
348 #define HDA_DSP_ADSPCS_CRST_SHIFT 0
349 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
350
351 /*
352 * Core run/stall - when set to '1' core is stalled
353 * CSTALL Mask for a given core mask pattern, cm
354 */
355 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
356 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
357
358 /*
359 * Set Power Active - when set to '1' turn cores on
360 * SPA Mask for a given core mask pattern, cm
361 */
362 #define HDA_DSP_ADSPCS_SPA_SHIFT 16
363 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
364
365 /*
366 * Current Power Active - power status of cores, set by hardware
367 * CPA Mask for a given core mask pattern, cm
368 */
369 #define HDA_DSP_ADSPCS_CPA_SHIFT 24
370 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
371
372 /*
373 * Mask for a given number of cores
374 * nc = number of supported cores
375 */
376 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
377
378 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
379 #define CNL_DSP_IPC_BASE 0xc0
380 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
381 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
382 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
383 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
384 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
385 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
386 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
387
388 /* HIPCI */
389 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
390 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
391
392 /* HIPCIE */
393 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
394 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
395
396 /* HIPCCTL */
397 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
398 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
399
400 /* HIPCT */
401 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
402 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
403
404 /* HIPCTDA */
405 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
406 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
407
408 /* HIPCTDD */
409 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
410
411 /* BDL */
412 #define HDA_DSP_BDL_SIZE 4096
413 #define HDA_DSP_MAX_BDL_ENTRIES \
414 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
415
416 /* Number of DAIs */
417 #define SOF_SKL_NUM_DAIS_NOCODEC 8
418
419 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
420 #define SOF_SKL_NUM_DAIS 15
421 #else
422 #define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC
423 #endif
424
425 /* Intel HD Audio SRAM Window 0*/
426 #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
427 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
428
429 /* Firmware status window */
430 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
431 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
432
433 /* Host Device Memory Space */
434 #define APL_SSP_BASE_OFFSET 0x2000
435 #define CNL_SSP_BASE_OFFSET 0x10000
436
437 /* Host Device Memory Size of a Single SSP */
438 #define SSP_DEV_MEM_SIZE 0x1000
439
440 /* SSP Count of the Platform */
441 #define APL_SSP_COUNT 6
442 #define CNL_SSP_COUNT 3
443 #define ICL_SSP_COUNT 6
444 #define TGL_SSP_COUNT 3
445 #define MTL_SSP_COUNT 3
446
447 /* SSP Registers */
448 #define SSP_SSC1_OFFSET 0x4
449 #define SSP_SET_SCLK_CONSUMER BIT(25)
450 #define SSP_SET_SFRM_CONSUMER BIT(24)
451 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
452
453 #define HDA_IDISP_ADDR 2
454 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
455
456 struct sof_intel_dsp_bdl {
457 __le32 addr_l;
458 __le32 addr_h;
459 __le32 size;
460 __le32 ioc;
461 } __attribute((packed));
462
463 #define SOF_HDA_PLAYBACK_STREAMS 16
464 #define SOF_HDA_CAPTURE_STREAMS 16
465 #define SOF_HDA_PLAYBACK 0
466 #define SOF_HDA_CAPTURE 1
467
468 /* stream flags */
469 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
470
471 /*
472 * Time in ms for opportunistic D0I3 entry delay.
473 * This has been deliberately chosen to be long to avoid race conditions.
474 * Could be optimized in future.
475 */
476 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000
477
478 /* HDA DSP D0 substate */
479 enum sof_hda_D0_substate {
480 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
481 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
482 };
483
484 /* represents DSP HDA controller frontend - i.e. host facing control */
485 struct sof_intel_hda_dev {
486 bool imrboot_supported;
487 bool skip_imr_boot;
488 bool booted_from_imr;
489
490 int boot_iteration;
491
492 struct hda_bus hbus;
493
494 /* hw config */
495 const struct sof_intel_dsp_desc *desc;
496
497 /* trace */
498 struct hdac_ext_stream *dtrace_stream;
499
500 /* if position update IPC needed */
501 u32 no_ipc_position;
502
503 /* the maximum number of streams (playback + capture) supported */
504 u32 stream_max;
505
506 /* PM related */
507 bool l1_disabled;/* is DMI link L1 disabled? */
508
509 /* DMIC device */
510 struct platform_device *dmic_dev;
511
512 /* delayed work to enter D0I3 opportunistically */
513 struct delayed_work d0i3_work;
514
515 /* ACPI information stored between scan and probe steps */
516 struct sdw_intel_acpi_info info;
517
518 /* sdw context allocated by SoundWire driver */
519 struct sdw_intel_ctx *sdw;
520
521 /* FW clock config, 0:HPRO, 1:LPRO */
522 bool clk_config_lpro;
523
524 wait_queue_head_t waitq;
525 bool code_loading;
526
527 /* Intel NHLT information */
528 struct nhlt_acpi_table *nhlt;
529
530 /*
531 * Pointing to the IPC message if immediate sending was not possible
532 * because the downlink communication channel was BUSY at the time.
533 * The message will be re-tried when the channel becomes free (the ACK
534 * is received from the DSP for the previous message)
535 */
536 struct snd_sof_ipc_msg *delayed_ipc_tx_msg;
537 };
538
sof_to_bus(struct snd_sof_dev * s)539 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
540 {
541 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
542
543 return &hda->hbus.core;
544 }
545
sof_to_hbus(struct snd_sof_dev * s)546 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
547 {
548 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
549
550 return &hda->hbus;
551 }
552
553 struct sof_intel_hda_stream {
554 struct snd_sof_dev *sdev;
555 struct hdac_ext_stream hext_stream;
556 struct sof_intel_stream sof_intel_stream;
557 int host_reserved; /* reserve host DMA channel */
558 u32 flags;
559 };
560
561 #define hstream_to_sof_hda_stream(hstream) \
562 container_of(hstream, struct sof_intel_hda_stream, hext_stream)
563
564 #define bus_to_sof_hda(bus) \
565 container_of(bus, struct sof_intel_hda_dev, hbus.core)
566
567 #define SOF_STREAM_SD_OFFSET(s) \
568 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
569 + SOF_HDA_ADSP_LOADER_BASE)
570
571 #define SOF_STREAM_SD_OFFSET_CRST 0x1
572
573 /*
574 * DSP Core services.
575 */
576 int hda_dsp_probe(struct snd_sof_dev *sdev);
577 int hda_dsp_remove(struct snd_sof_dev *sdev);
578 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
579 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
580 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
581 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
582 unsigned int core_mask);
583 int hda_power_down_dsp(struct snd_sof_dev *sdev);
584 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
585 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
586 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
587 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask);
588
589 int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
590 const struct sof_dsp_power_state *target_state);
591 int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
592 const struct sof_dsp_power_state *target_state);
593
594 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
595 int hda_dsp_resume(struct snd_sof_dev *sdev);
596 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
597 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
598 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
599 int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev);
600 int hda_dsp_shutdown(struct snd_sof_dev *sdev);
601 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
602 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
603 void hda_ipc_dump(struct snd_sof_dev *sdev);
604 void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
605 void hda_dsp_d0i3_work(struct work_struct *work);
606 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
607
608 /*
609 * DSP PCM Operations.
610 */
611 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
612 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
613 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
614 struct snd_pcm_substream *substream);
615 int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
616 struct snd_pcm_substream *substream);
617 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
618 struct snd_pcm_substream *substream,
619 struct snd_pcm_hw_params *params,
620 struct snd_sof_platform_stream_params *platform_params);
621 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
622 struct snd_pcm_substream *substream);
623 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
624 struct snd_pcm_substream *substream, int cmd);
625 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
626 struct snd_pcm_substream *substream);
627 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
628
629 /*
630 * DSP Stream Operations.
631 */
632
633 int hda_dsp_stream_init(struct snd_sof_dev *sdev);
634 void hda_dsp_stream_free(struct snd_sof_dev *sdev);
635 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
636 struct hdac_ext_stream *hext_stream,
637 struct snd_dma_buffer *dmab,
638 struct snd_pcm_hw_params *params);
639 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
640 struct hdac_ext_stream *hext_stream,
641 struct snd_dma_buffer *dmab,
642 struct snd_pcm_hw_params *params);
643 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
644 struct hdac_ext_stream *hext_stream, int cmd);
645 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
646 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
647 struct snd_dma_buffer *dmab,
648 struct hdac_stream *hstream);
649 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
650 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
651
652 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
653 int direction, bool can_sleep);
654
655 struct hdac_ext_stream *
656 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
657 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
658 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
659 struct hdac_ext_stream *hext_stream,
660 int enable, u32 size);
661
662 int hda_ipc_msg_data(struct snd_sof_dev *sdev,
663 struct snd_sof_pcm_stream *sps,
664 void *p, size_t sz);
665 int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
666 struct snd_sof_pcm_stream *sps,
667 size_t posn_offset);
668
669 /*
670 * DSP IPC Operations.
671 */
672 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
673 struct snd_sof_ipc_msg *msg);
674 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
675 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
676 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
677
678 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
679 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
680
681 /*
682 * DSP Code loader.
683 */
684 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
685 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
686 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
687 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
688 unsigned int size, struct snd_dma_buffer *dmab,
689 int direction);
690 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
691 struct hdac_ext_stream *hext_stream);
692 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
693 #define HDA_CL_STREAM_FORMAT 0x40
694
695 /* pre and post fw run ops */
696 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
697 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
698
699 /* parse platform specific ext manifest ops */
700 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
701 const struct sof_ext_man_elem_header *hdr);
702
703 /*
704 * HDA Controller Operations.
705 */
706 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
707 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
708 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
709 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
710 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
711 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
712 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev);
713 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
714 /*
715 * HDA bus operations.
716 */
717 void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev);
718 void sof_hda_bus_exit(struct snd_sof_dev *sdev);
719
720 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
721 /*
722 * HDA Codec operations.
723 */
724 void hda_codec_probe_bus(struct snd_sof_dev *sdev);
725 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
726 void hda_codec_jack_check(struct snd_sof_dev *sdev);
727 void hda_codec_check_for_state_change(struct snd_sof_dev *sdev);
728 void hda_codec_init_cmd_io(struct snd_sof_dev *sdev);
729 void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev);
730 void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev);
731 void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev);
732 void hda_codec_detect_mask(struct snd_sof_dev *sdev);
733 void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev);
734 bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev);
735 void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status);
736 void hda_codec_device_remove(struct snd_sof_dev *sdev);
737
738 #else
739
hda_codec_probe_bus(struct snd_sof_dev * sdev)740 static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { }
hda_codec_jack_wake_enable(struct snd_sof_dev * sdev,bool enable)741 static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { }
hda_codec_jack_check(struct snd_sof_dev * sdev)742 static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { }
hda_codec_check_for_state_change(struct snd_sof_dev * sdev)743 static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { }
hda_codec_init_cmd_io(struct snd_sof_dev * sdev)744 static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_resume_cmd_io(struct snd_sof_dev * sdev)745 static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_stop_cmd_io(struct snd_sof_dev * sdev)746 static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_suspend_cmd_io(struct snd_sof_dev * sdev)747 static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { }
hda_codec_detect_mask(struct snd_sof_dev * sdev)748 static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { }
hda_codec_rirb_status_clear(struct snd_sof_dev * sdev)749 static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { }
hda_codec_check_rirb_status(struct snd_sof_dev * sdev)750 static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; }
hda_codec_set_codec_wakeup(struct snd_sof_dev * sdev,bool status)751 static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { }
hda_codec_device_remove(struct snd_sof_dev * sdev)752 static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { }
753
754 #endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
755
756 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
757
758 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
759 int hda_codec_i915_init(struct snd_sof_dev *sdev);
760 int hda_codec_i915_exit(struct snd_sof_dev *sdev);
761
762 #else
763
hda_codec_i915_display_power(struct snd_sof_dev * sdev,bool enable)764 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { }
hda_codec_i915_init(struct snd_sof_dev * sdev)765 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
hda_codec_i915_exit(struct snd_sof_dev * sdev)766 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
767
768 #endif
769
770 /*
771 * Trace Control.
772 */
773 int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
774 struct sof_ipc_dma_trace_params_ext *dtrace_params);
775 int hda_dsp_trace_release(struct snd_sof_dev *sdev);
776 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
777
778 /*
779 * SoundWire support
780 */
781 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
782
783 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev);
784 int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev);
785 int hda_sdw_startup(struct snd_sof_dev *sdev);
786 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable);
787 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
788 bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev);
789 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
790 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
791
792 #else
793
hda_sdw_check_lcount_common(struct snd_sof_dev * sdev)794 static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
795 {
796 return 0;
797 }
798
hda_sdw_check_lcount_ext(struct snd_sof_dev * sdev)799 static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
800 {
801 return 0;
802 }
803
hda_sdw_startup(struct snd_sof_dev * sdev)804 static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
805 {
806 return 0;
807 }
808
hda_common_enable_sdw_irq(struct snd_sof_dev * sdev,bool enable)809 static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
810 {
811 }
812
hda_sdw_int_enable(struct snd_sof_dev * sdev,bool enable)813 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
814 {
815 }
816
hda_sdw_check_wakeen_irq_common(struct snd_sof_dev * sdev)817 static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
818 {
819 return false;
820 }
821
hda_sdw_process_wakeen(struct snd_sof_dev * sdev)822 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
823 {
824 }
825
hda_common_check_sdw_irq(struct snd_sof_dev * sdev)826 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
827 {
828 return false;
829 }
830
831 #endif
832
833 int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream,
834 struct snd_pcm_hw_params *params,
835 struct snd_soc_dai *cpu_dai,
836 int link_id);
837
838 int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream,
839 struct snd_soc_dai *cpu_dai,
840 int link_id);
841
842 int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd,
843 struct snd_soc_dai *cpu_dai);
844
845 /* common dai driver */
846 extern struct snd_soc_dai_driver skl_dai[];
847 int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
848
849 /*
850 * Platform Specific HW abstraction Ops.
851 */
852 extern struct snd_sof_dsp_ops sof_hda_common_ops;
853
854 extern struct snd_sof_dsp_ops sof_skl_ops;
855 int sof_skl_ops_init(struct snd_sof_dev *sdev);
856 extern struct snd_sof_dsp_ops sof_apl_ops;
857 int sof_apl_ops_init(struct snd_sof_dev *sdev);
858 extern struct snd_sof_dsp_ops sof_cnl_ops;
859 int sof_cnl_ops_init(struct snd_sof_dev *sdev);
860 extern struct snd_sof_dsp_ops sof_tgl_ops;
861 int sof_tgl_ops_init(struct snd_sof_dev *sdev);
862 extern struct snd_sof_dsp_ops sof_icl_ops;
863 int sof_icl_ops_init(struct snd_sof_dev *sdev);
864 extern struct snd_sof_dsp_ops sof_mtl_ops;
865 int sof_mtl_ops_init(struct snd_sof_dev *sdev);
866 extern struct snd_sof_dsp_ops sof_lnl_ops;
867 int sof_lnl_ops_init(struct snd_sof_dev *sdev);
868
869 extern const struct sof_intel_dsp_desc skl_chip_info;
870 extern const struct sof_intel_dsp_desc apl_chip_info;
871 extern const struct sof_intel_dsp_desc cnl_chip_info;
872 extern const struct sof_intel_dsp_desc icl_chip_info;
873 extern const struct sof_intel_dsp_desc tgl_chip_info;
874 extern const struct sof_intel_dsp_desc tglh_chip_info;
875 extern const struct sof_intel_dsp_desc ehl_chip_info;
876 extern const struct sof_intel_dsp_desc jsl_chip_info;
877 extern const struct sof_intel_dsp_desc adls_chip_info;
878 extern const struct sof_intel_dsp_desc mtl_chip_info;
879 extern const struct sof_intel_dsp_desc lnl_chip_info;
880
881 /* Probes support */
882 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
883 int hda_probes_register(struct snd_sof_dev *sdev);
884 void hda_probes_unregister(struct snd_sof_dev *sdev);
885 #else
hda_probes_register(struct snd_sof_dev * sdev)886 static inline int hda_probes_register(struct snd_sof_dev *sdev)
887 {
888 return 0;
889 }
890
hda_probes_unregister(struct snd_sof_dev * sdev)891 static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
892 {
893 }
894 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
895
896 /* SOF client registration for HDA platforms */
897 int hda_register_clients(struct snd_sof_dev *sdev);
898 void hda_unregister_clients(struct snd_sof_dev *sdev);
899
900 /* machine driver select */
901 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
902 void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
903 struct snd_sof_dev *sdev);
904
905 /* PCI driver selection and probe */
906 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
907
908 struct snd_sof_dai;
909 struct sof_ipc_dai_config;
910
911 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */
912 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */
913 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */
914
915 extern int sof_hda_position_quirk;
916
917 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
918 void hda_ops_free(struct snd_sof_dev *sdev);
919
920 /* SKL/KBL */
921 int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
922 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
923
924 /* IPC4 */
925 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
926 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
927 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
928 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev);
929 void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev,
930 struct snd_sof_ipc_msg *msg);
931 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
932 void hda_ipc4_dump(struct snd_sof_dev *sdev);
933 extern struct sdw_intel_ops sdw_callback;
934
935 struct sof_ipc4_fw_library;
936 int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
937 struct sof_ipc4_fw_library *fw_lib, bool reload);
938
939 /**
940 * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise
941 * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream
942 * @assign_hext_stream: Function pointer to assign a hdac_ext_stream
943 * @release_hext_stream: Function pointer to release the hdac_ext_stream
944 * @setup_hext_stream: Function pointer for hdac_ext_stream setup
945 * @reset_hext_stream: Function pointer for hdac_ext_stream reset
946 * @pre_trigger: Function pointer for DAI DMA pre-trigger actions
947 * @trigger: Function pointer for DAI DMA trigger actions
948 * @post_trigger: Function pointer for DAI DMA post-trigger actions
949 * @codec_dai_set_stream: Function pointer to set codec-side stream information
950 * @calc_stream_format: Function pointer to determine stream format from hw_params and
951 * for HDaudio codec DAI from the .sig bits
952 * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV
953 * for legacy HDaudio links or program HDaudio Extended Link registers.
954 */
955 struct hda_dai_widget_dma_ops {
956 struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev,
957 struct snd_soc_dai *cpu_dai,
958 struct snd_pcm_substream *substream);
959 struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev,
960 struct snd_soc_dai *cpu_dai,
961 struct snd_pcm_substream *substream);
962 void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
963 struct snd_pcm_substream *substream);
964 void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
965 unsigned int format_val);
966 void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream);
967 int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
968 struct snd_pcm_substream *substream, int cmd);
969 int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
970 struct snd_pcm_substream *substream, int cmd);
971 int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
972 struct snd_pcm_substream *substream, int cmd);
973 void (*codec_dai_set_stream)(struct snd_sof_dev *sdev,
974 struct snd_pcm_substream *substream,
975 struct hdac_stream *hstream);
976 unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev,
977 struct snd_pcm_substream *substream,
978 struct snd_pcm_hw_params *params);
979 struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev,
980 struct snd_pcm_substream *substream);
981 };
982
983 const struct hda_dai_widget_dma_ops *
984 hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget);
985 int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags,
986 struct snd_sof_dai_config_data *data);
987 int hda_link_dma_cleanup(struct snd_pcm_substream *substream, struct hdac_ext_stream *hext_stream,
988 struct snd_soc_dai *cpu_dai);
989
990 #endif
991