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/linux-6.6.21/drivers/staging/axis-fifo/
DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
37 - xlnx,rx-fifo-depth: Depth of RX FIFO in words
45 - xlnx,tx-fifo-depth: Depth of TX FIFO in words
51 - xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
54 - xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
/linux-6.6.21/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt24 12: UTXINT1 UART1 transmit FIFO half empty
25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
30 18: SS2TX SSI2 transmit FIFO less than half empty
31 28: UTXINT2 UART2 transmit FIFO half empty
32 29: URXINT2 UART2 receive FIFO half full
/linux-6.6.21/Documentation/devicetree/bindings/display/bridge/
Dsil,sii9022.yaml63 Each integer indicates which I2S pin is connected to which audio FIFO.
64 The first integer selects the I2S audio pin for the first audio FIFO#0
65 (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
67 connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
68 mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
70 FIFO#0.
/linux-6.6.21/Documentation/networking/device_drivers/can/freescale/
Dflexcan.rst15 - FIFO
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
/linux-6.6.21/Documentation/devicetree/bindings/net/can/
Dbosch,m_can.yaml57 and each element(e.g Rx FIFO or Tx Buffer and etc) number
67 are used to specify how many elements are used for each FIFO/Buffer.
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
92 - description: Rx FIFO 0 0-64 elements / 0-1152 words
95 - description: Rx FIFO 1 0-64 elements / 0-1152 words
101 - description: Tx Event FIFO 0-32 elements / 0-64 words
/linux-6.6.21/Documentation/devicetree/bindings/dma/
Dst,stm32-dma.yaml34 -bit 0-1: DMA FIFO threshold selection
35 0x0: 1/4 full FIFO
36 0x1: 1/2 full FIFO
37 0x2: 3/4 full FIFO
38 0x3: full FIFO
40 0x0: FIFO mode with threshold selectable with bit 0-1
42 from/to the memory, FIFO is bypassed.
Datmel-dma.txt31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
/linux-6.6.21/Documentation/accel/qaic/
Daic100.rst241 FIFO is the request FIFO. The other FIFO is the response FIFO.
245 * Request FIFO head pointer (offset 0x0). Read only by the host. Indicates the
246 latest item in the FIFO the device has consumed.
247 * Request FIFO tail pointer (offset 0x4). Read/write by the host. Host
248 increments this register to add new items to the FIFO.
249 * Response FIFO head pointer (offset 0x8). Read/write by the host. Indicates
250 the latest item in the FIFO the host has consumed.
251 * Response FIFO tail pointer (offset 0xc). Read only by the host. Device
252 increments this register to add new items to the FIFO.
254 The values in each register are indexes in the FIFO. To get the location of the
[all …]
/linux-6.6.21/drivers/video/fbdev/riva/
Driva_hw.c1351 LOAD_FIXED_STATE(nv4,FIFO); in UpdateFifoState()
1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1362 LOAD_FIXED_STATE(nv10,FIFO); in UpdateFifoState()
1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1645 LOAD_FIXED_STATE(Riva,FIFO); in LoadStateExt()
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/serial/
Dmvebu-uart.txt7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
8 FIFO), called also UART1.
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
11 accesses to the FIFO), called also UART2.
/linux-6.6.21/Documentation/spi/
Dpxa2xx.rst15 The driver is built around a &struct spi_message FIFO serviced by kernel
16 thread. The kernel thread, spi_pump_messages(), drives message FIFO and
107 used to configure the SSP hardware FIFO. These fields are critical to the
109 FIFO overruns (especially in PIO mode transfers). Good default values are::
124 trailing bytes in the SSP receiver FIFO. The correct value for this field is
144 .tx_threshold = 8, /* SSP hardware FIFO threshold */
145 .rx_threshold = 8, /* SSP hardware FIFO threshold */
151 .tx_threshold = 8, /* SSP hardware FIFO threshold */
152 .rx_threshold = 8, /* SSP hardware FIFO threshold */
/linux-6.6.21/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5121-psc.txt8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
19 PSC FIFO Controller and b is a field that represents an
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
/linux-6.6.21/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt85 Ethernet FIFO ECC
93 NAND FIFO ECC
101 DMA FIFO ECC
109 USB FIFO ECC
117 QSPI FIFO ECC
125 SDMMC FIFO ECC
268 Ethernet FIFO ECC
275 NAND FIFO ECC
282 DMA FIFO ECC
289 USB FIFO ECC
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/sound/
Ddavinci-mcasp-audio.yaml83 0 disables the FIFO use
84 if property is missing, then also FIFO use is disabled
90 0 disables the FIFO use
91 if property is missing, then also FIFO use is disabled
Dsamsung-i2s.yaml22 secondary FIFO, s/w reset control and internal mux for root clock
26 playback, stereo channel capture, secondary FIFO using internal
33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
42 capture, secondary FIFO using external DMA, s/w reset control,
/linux-6.6.21/drivers/scsi/aic7xxx/
Daic79xx.seq169 * Since this status did not consume a FIFO, we have to
171 * to this transaction. There are two states that a FIFO still
174 * 1) Configured and draining to the host, with a FIFO handler.
177 * Case 1 can be detected by noticing a non-zero FIFO active
179 * the FIFO to complete the SCB.
182 * pointers for this same context in the other FIFO. So, if
308 * The FIFO use count field is shared with the
583 * Allocate a FIFO for a non-packetized transaction.
585 * can allocate a FIFO for a non-packetized transaction.
589 * Do whatever work is required to free a FIFO.
[all …]
/linux-6.6.21/arch/sparc/include/asm/
Dfloppy_64.h449 #define FIFO (port + 5) macro
468 sun_pci_fd_out_byte(port, 0x08, FIFO); in sun_pci_fd_sensei()
479 result[i++] = inb(FIFO); in sun_pci_fd_sensei()
514 sun_pci_fd_out_byte(port, 0x07, FIFO); in sun_pci_fd_test_drive()
515 sun_pci_fd_out_byte(port, drive & 0x03, FIFO); in sun_pci_fd_test_drive()
530 #undef FIFO
/linux-6.6.21/drivers/video/fbdev/nvidia/
Dnv_local.h92 NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
/linux-6.6.21/arch/powerpc/platforms/512x/
DKconfig14 tristate "MPC512x LocalPlus Bus FIFO driver"
17 Enable support for Freescale MPC512x LocalPlus Bus FIFO (SCLPC).
/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/
Dqca,ath79-ddr-controller.yaml14 flush the FIFO between various devices and the DDR. This is mainly used by
15 the IRQ controller to flush the FIFO before running the interrupt handler of
/linux-6.6.21/drivers/char/tpm/
DKconfig48 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface"
53 TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO
59 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
65 TCG TIS 1.3 TPM specification (TPM1.2) or the TCG PTP FIFO
78 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
90 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
95 TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO
/linux-6.6.21/arch/arm/include/debug/
Dsamsung.S56 @ FIFO enabled...
80 @ FIFO enabled...
/linux-6.6.21/sound/soc/cirrus/
DKconfig24 Underflow of internal I2S controller FIFO could confuse the
28 fills FIFO with zeroes.
/linux-6.6.21/Documentation/devicetree/bindings/spi/
Dnvidia,tegra114-spi.yaml47 - description: DMA channel for the reception FIFO
48 - description: DMA channel for the transmission FIFO

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