1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2015 Regents of the University of California
4  */
5 
6 #ifndef _ASM_RISCV_CSR_H
7 #define _ASM_RISCV_CSR_H
8 
9 #include <asm/asm.h>
10 #include <linux/bits.h>
11 
12 /* Status register flags */
13 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
20 
21 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF	_AC(0x00000000, UL)
23 #define SR_FS_INITIAL	_AC(0x00002000, UL)
24 #define SR_FS_CLEAN	_AC(0x00004000, UL)
25 #define SR_FS_DIRTY	_AC(0x00006000, UL)
26 
27 #define SR_VS		_AC(0x00000600, UL) /* Vector Status */
28 #define SR_VS_OFF	_AC(0x00000000, UL)
29 #define SR_VS_INITIAL	_AC(0x00000200, UL)
30 #define SR_VS_CLEAN	_AC(0x00000400, UL)
31 #define SR_VS_DIRTY	_AC(0x00000600, UL)
32 
33 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
34 #define SR_XS_OFF	_AC(0x00000000, UL)
35 #define SR_XS_INITIAL	_AC(0x00008000, UL)
36 #define SR_XS_CLEAN	_AC(0x00010000, UL)
37 #define SR_XS_DIRTY	_AC(0x00018000, UL)
38 
39 #define SR_FS_VS	(SR_FS | SR_VS) /* Vector and Floating-Point Unit */
40 
41 #ifndef CONFIG_64BIT
42 #define SR_SD		_AC(0x80000000, UL) /* FS/VS/XS dirty */
43 #else
44 #define SR_SD		_AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
45 #endif
46 
47 #ifdef CONFIG_64BIT
48 #define SR_UXL		_AC(0x300000000, UL) /* XLEN mask for U-mode */
49 #define SR_UXL_32	_AC(0x100000000, UL) /* XLEN = 32 for U-mode */
50 #define SR_UXL_64	_AC(0x200000000, UL) /* XLEN = 64 for U-mode */
51 #endif
52 
53 /* SATP flags */
54 #ifndef CONFIG_64BIT
55 #define SATP_PPN	_AC(0x003FFFFF, UL)
56 #define SATP_MODE_32	_AC(0x80000000, UL)
57 #define SATP_MODE_SHIFT	31
58 #define SATP_ASID_BITS	9
59 #define SATP_ASID_SHIFT	22
60 #define SATP_ASID_MASK	_AC(0x1FF, UL)
61 #else
62 #define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
63 #define SATP_MODE_39	_AC(0x8000000000000000, UL)
64 #define SATP_MODE_48	_AC(0x9000000000000000, UL)
65 #define SATP_MODE_57	_AC(0xa000000000000000, UL)
66 #define SATP_MODE_SHIFT	60
67 #define SATP_ASID_BITS	16
68 #define SATP_ASID_SHIFT	44
69 #define SATP_ASID_MASK	_AC(0xFFFF, UL)
70 #endif
71 
72 /* Exception cause high bit - is an interrupt if set */
73 #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
74 
75 /* Interrupt causes (minus the high bit) */
76 #define IRQ_S_SOFT		1
77 #define IRQ_VS_SOFT		2
78 #define IRQ_M_SOFT		3
79 #define IRQ_S_TIMER		5
80 #define IRQ_VS_TIMER		6
81 #define IRQ_M_TIMER		7
82 #define IRQ_S_EXT		9
83 #define IRQ_VS_EXT		10
84 #define IRQ_M_EXT		11
85 #define IRQ_S_GEXT		12
86 #define IRQ_PMU_OVF		13
87 #define IRQ_LOCAL_MAX		(IRQ_PMU_OVF + 1)
88 #define IRQ_LOCAL_MASK		GENMASK((IRQ_LOCAL_MAX - 1), 0)
89 
90 /* Exception causes */
91 #define EXC_INST_MISALIGNED	0
92 #define EXC_INST_ACCESS		1
93 #define EXC_INST_ILLEGAL	2
94 #define EXC_BREAKPOINT		3
95 #define EXC_LOAD_MISALIGNED	4
96 #define EXC_LOAD_ACCESS		5
97 #define EXC_STORE_MISALIGNED	6
98 #define EXC_STORE_ACCESS	7
99 #define EXC_SYSCALL		8
100 #define EXC_HYPERVISOR_SYSCALL	9
101 #define EXC_SUPERVISOR_SYSCALL	10
102 #define EXC_INST_PAGE_FAULT	12
103 #define EXC_LOAD_PAGE_FAULT	13
104 #define EXC_STORE_PAGE_FAULT	15
105 #define EXC_INST_GUEST_PAGE_FAULT	20
106 #define EXC_LOAD_GUEST_PAGE_FAULT	21
107 #define EXC_VIRTUAL_INST_FAULT		22
108 #define EXC_STORE_GUEST_PAGE_FAULT	23
109 
110 /* PMP configuration */
111 #define PMP_R			0x01
112 #define PMP_W			0x02
113 #define PMP_X			0x04
114 #define PMP_A			0x18
115 #define PMP_A_TOR		0x08
116 #define PMP_A_NA4		0x10
117 #define PMP_A_NAPOT		0x18
118 #define PMP_L			0x80
119 
120 /* HSTATUS flags */
121 #ifdef CONFIG_64BIT
122 #define HSTATUS_VSXL		_AC(0x300000000, UL)
123 #define HSTATUS_VSXL_SHIFT	32
124 #endif
125 #define HSTATUS_VTSR		_AC(0x00400000, UL)
126 #define HSTATUS_VTW		_AC(0x00200000, UL)
127 #define HSTATUS_VTVM		_AC(0x00100000, UL)
128 #define HSTATUS_VGEIN		_AC(0x0003f000, UL)
129 #define HSTATUS_VGEIN_SHIFT	12
130 #define HSTATUS_HU		_AC(0x00000200, UL)
131 #define HSTATUS_SPVP		_AC(0x00000100, UL)
132 #define HSTATUS_SPV		_AC(0x00000080, UL)
133 #define HSTATUS_GVA		_AC(0x00000040, UL)
134 #define HSTATUS_VSBE		_AC(0x00000020, UL)
135 
136 /* HGATP flags */
137 #define HGATP_MODE_OFF		_AC(0, UL)
138 #define HGATP_MODE_SV32X4	_AC(1, UL)
139 #define HGATP_MODE_SV39X4	_AC(8, UL)
140 #define HGATP_MODE_SV48X4	_AC(9, UL)
141 #define HGATP_MODE_SV57X4	_AC(10, UL)
142 
143 #define HGATP32_MODE_SHIFT	31
144 #define HGATP32_VMID_SHIFT	22
145 #define HGATP32_VMID		GENMASK(28, 22)
146 #define HGATP32_PPN		GENMASK(21, 0)
147 
148 #define HGATP64_MODE_SHIFT	60
149 #define HGATP64_VMID_SHIFT	44
150 #define HGATP64_VMID		GENMASK(57, 44)
151 #define HGATP64_PPN		GENMASK(43, 0)
152 
153 #define HGATP_PAGE_SHIFT	12
154 
155 #ifdef CONFIG_64BIT
156 #define HGATP_PPN		HGATP64_PPN
157 #define HGATP_VMID_SHIFT	HGATP64_VMID_SHIFT
158 #define HGATP_VMID		HGATP64_VMID
159 #define HGATP_MODE_SHIFT	HGATP64_MODE_SHIFT
160 #else
161 #define HGATP_PPN		HGATP32_PPN
162 #define HGATP_VMID_SHIFT	HGATP32_VMID_SHIFT
163 #define HGATP_VMID		HGATP32_VMID
164 #define HGATP_MODE_SHIFT	HGATP32_MODE_SHIFT
165 #endif
166 
167 /* VSIP & HVIP relation */
168 #define VSIP_TO_HVIP_SHIFT	(IRQ_VS_SOFT - IRQ_S_SOFT)
169 #define VSIP_VALID_MASK		((_AC(1, UL) << IRQ_S_SOFT) | \
170 				 (_AC(1, UL) << IRQ_S_TIMER) | \
171 				 (_AC(1, UL) << IRQ_S_EXT))
172 
173 /* AIA CSR bits */
174 #define TOPI_IID_SHIFT		16
175 #define TOPI_IID_MASK		GENMASK(11, 0)
176 #define TOPI_IPRIO_MASK		GENMASK(7, 0)
177 #define TOPI_IPRIO_BITS		8
178 
179 #define TOPEI_ID_SHIFT		16
180 #define TOPEI_ID_MASK		GENMASK(10, 0)
181 #define TOPEI_PRIO_MASK		GENMASK(10, 0)
182 
183 #define ISELECT_IPRIO0		0x30
184 #define ISELECT_IPRIO15		0x3f
185 #define ISELECT_MASK		GENMASK(8, 0)
186 
187 #define HVICTL_VTI		BIT(30)
188 #define HVICTL_IID		GENMASK(27, 16)
189 #define HVICTL_IID_SHIFT	16
190 #define HVICTL_DPR		BIT(9)
191 #define HVICTL_IPRIOM		BIT(8)
192 #define HVICTL_IPRIO		GENMASK(7, 0)
193 
194 /* xENVCFG flags */
195 #define ENVCFG_STCE			(_AC(1, ULL) << 63)
196 #define ENVCFG_PBMTE			(_AC(1, ULL) << 62)
197 #define ENVCFG_CBZE			(_AC(1, UL) << 7)
198 #define ENVCFG_CBCFE			(_AC(1, UL) << 6)
199 #define ENVCFG_CBIE_SHIFT		4
200 #define ENVCFG_CBIE			(_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)
201 #define ENVCFG_CBIE_ILL			_AC(0x0, UL)
202 #define ENVCFG_CBIE_FLUSH		_AC(0x1, UL)
203 #define ENVCFG_CBIE_INV			_AC(0x3, UL)
204 #define ENVCFG_FIOM			_AC(0x1, UL)
205 
206 /* symbolic CSR names: */
207 #define CSR_CYCLE		0xc00
208 #define CSR_TIME		0xc01
209 #define CSR_INSTRET		0xc02
210 #define CSR_HPMCOUNTER3		0xc03
211 #define CSR_HPMCOUNTER4		0xc04
212 #define CSR_HPMCOUNTER5		0xc05
213 #define CSR_HPMCOUNTER6		0xc06
214 #define CSR_HPMCOUNTER7		0xc07
215 #define CSR_HPMCOUNTER8		0xc08
216 #define CSR_HPMCOUNTER9		0xc09
217 #define CSR_HPMCOUNTER10	0xc0a
218 #define CSR_HPMCOUNTER11	0xc0b
219 #define CSR_HPMCOUNTER12	0xc0c
220 #define CSR_HPMCOUNTER13	0xc0d
221 #define CSR_HPMCOUNTER14	0xc0e
222 #define CSR_HPMCOUNTER15	0xc0f
223 #define CSR_HPMCOUNTER16	0xc10
224 #define CSR_HPMCOUNTER17	0xc11
225 #define CSR_HPMCOUNTER18	0xc12
226 #define CSR_HPMCOUNTER19	0xc13
227 #define CSR_HPMCOUNTER20	0xc14
228 #define CSR_HPMCOUNTER21	0xc15
229 #define CSR_HPMCOUNTER22	0xc16
230 #define CSR_HPMCOUNTER23	0xc17
231 #define CSR_HPMCOUNTER24	0xc18
232 #define CSR_HPMCOUNTER25	0xc19
233 #define CSR_HPMCOUNTER26	0xc1a
234 #define CSR_HPMCOUNTER27	0xc1b
235 #define CSR_HPMCOUNTER28	0xc1c
236 #define CSR_HPMCOUNTER29	0xc1d
237 #define CSR_HPMCOUNTER30	0xc1e
238 #define CSR_HPMCOUNTER31	0xc1f
239 #define CSR_CYCLEH		0xc80
240 #define CSR_TIMEH		0xc81
241 #define CSR_INSTRETH		0xc82
242 #define CSR_HPMCOUNTER3H	0xc83
243 #define CSR_HPMCOUNTER4H	0xc84
244 #define CSR_HPMCOUNTER5H	0xc85
245 #define CSR_HPMCOUNTER6H	0xc86
246 #define CSR_HPMCOUNTER7H	0xc87
247 #define CSR_HPMCOUNTER8H	0xc88
248 #define CSR_HPMCOUNTER9H	0xc89
249 #define CSR_HPMCOUNTER10H	0xc8a
250 #define CSR_HPMCOUNTER11H	0xc8b
251 #define CSR_HPMCOUNTER12H	0xc8c
252 #define CSR_HPMCOUNTER13H	0xc8d
253 #define CSR_HPMCOUNTER14H	0xc8e
254 #define CSR_HPMCOUNTER15H	0xc8f
255 #define CSR_HPMCOUNTER16H	0xc90
256 #define CSR_HPMCOUNTER17H	0xc91
257 #define CSR_HPMCOUNTER18H	0xc92
258 #define CSR_HPMCOUNTER19H	0xc93
259 #define CSR_HPMCOUNTER20H	0xc94
260 #define CSR_HPMCOUNTER21H	0xc95
261 #define CSR_HPMCOUNTER22H	0xc96
262 #define CSR_HPMCOUNTER23H	0xc97
263 #define CSR_HPMCOUNTER24H	0xc98
264 #define CSR_HPMCOUNTER25H	0xc99
265 #define CSR_HPMCOUNTER26H	0xc9a
266 #define CSR_HPMCOUNTER27H	0xc9b
267 #define CSR_HPMCOUNTER28H	0xc9c
268 #define CSR_HPMCOUNTER29H	0xc9d
269 #define CSR_HPMCOUNTER30H	0xc9e
270 #define CSR_HPMCOUNTER31H	0xc9f
271 
272 #define CSR_SSCOUNTOVF		0xda0
273 
274 #define CSR_SSTATUS		0x100
275 #define CSR_SIE			0x104
276 #define CSR_STVEC		0x105
277 #define CSR_SCOUNTEREN		0x106
278 #define CSR_SSCRATCH		0x140
279 #define CSR_SEPC		0x141
280 #define CSR_SCAUSE		0x142
281 #define CSR_STVAL		0x143
282 #define CSR_SIP			0x144
283 #define CSR_SATP		0x180
284 
285 #define CSR_STIMECMP		0x14D
286 #define CSR_STIMECMPH		0x15D
287 
288 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
289 #define CSR_SISELECT		0x150
290 #define CSR_SIREG		0x151
291 
292 /* Supervisor-Level Interrupts (AIA) */
293 #define CSR_STOPEI		0x15c
294 #define CSR_STOPI		0xdb0
295 
296 /* Supervisor-Level High-Half CSRs (AIA) */
297 #define CSR_SIEH		0x114
298 #define CSR_SIPH		0x154
299 
300 #define CSR_VSSTATUS		0x200
301 #define CSR_VSIE		0x204
302 #define CSR_VSTVEC		0x205
303 #define CSR_VSSCRATCH		0x240
304 #define CSR_VSEPC		0x241
305 #define CSR_VSCAUSE		0x242
306 #define CSR_VSTVAL		0x243
307 #define CSR_VSIP		0x244
308 #define CSR_VSATP		0x280
309 #define CSR_VSTIMECMP		0x24D
310 #define CSR_VSTIMECMPH		0x25D
311 
312 #define CSR_HSTATUS		0x600
313 #define CSR_HEDELEG		0x602
314 #define CSR_HIDELEG		0x603
315 #define CSR_HIE			0x604
316 #define CSR_HTIMEDELTA		0x605
317 #define CSR_HCOUNTEREN		0x606
318 #define CSR_HGEIE		0x607
319 #define CSR_HENVCFG		0x60a
320 #define CSR_HTIMEDELTAH		0x615
321 #define CSR_HENVCFGH		0x61a
322 #define CSR_HTVAL		0x643
323 #define CSR_HIP			0x644
324 #define CSR_HVIP		0x645
325 #define CSR_HTINST		0x64a
326 #define CSR_HGATP		0x680
327 #define CSR_HGEIP		0xe12
328 
329 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
330 #define CSR_HVIEN		0x608
331 #define CSR_HVICTL		0x609
332 #define CSR_HVIPRIO1		0x646
333 #define CSR_HVIPRIO2		0x647
334 
335 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
336 #define CSR_VSISELECT		0x250
337 #define CSR_VSIREG		0x251
338 
339 /* VS-Level Interrupts (H-extension with AIA) */
340 #define CSR_VSTOPEI		0x25c
341 #define CSR_VSTOPI		0xeb0
342 
343 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
344 #define CSR_HIDELEGH		0x613
345 #define CSR_HVIENH		0x618
346 #define CSR_HVIPH		0x655
347 #define CSR_HVIPRIO1H		0x656
348 #define CSR_HVIPRIO2H		0x657
349 #define CSR_VSIEH		0x214
350 #define CSR_VSIPH		0x254
351 
352 #define CSR_MSTATUS		0x300
353 #define CSR_MISA		0x301
354 #define CSR_MIDELEG		0x303
355 #define CSR_MIE			0x304
356 #define CSR_MTVEC		0x305
357 #define CSR_MENVCFG		0x30a
358 #define CSR_MENVCFGH		0x31a
359 #define CSR_MSCRATCH		0x340
360 #define CSR_MEPC		0x341
361 #define CSR_MCAUSE		0x342
362 #define CSR_MTVAL		0x343
363 #define CSR_MIP			0x344
364 #define CSR_PMPCFG0		0x3a0
365 #define CSR_PMPADDR0		0x3b0
366 #define CSR_MVENDORID		0xf11
367 #define CSR_MARCHID		0xf12
368 #define CSR_MIMPID		0xf13
369 #define CSR_MHARTID		0xf14
370 
371 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
372 #define CSR_MISELECT		0x350
373 #define CSR_MIREG		0x351
374 
375 /* Machine-Level Interrupts (AIA) */
376 #define CSR_MTOPEI		0x35c
377 #define CSR_MTOPI		0xfb0
378 
379 /* Virtual Interrupts for Supervisor Level (AIA) */
380 #define CSR_MVIEN		0x308
381 #define CSR_MVIP		0x309
382 
383 /* Machine-Level High-Half CSRs (AIA) */
384 #define CSR_MIDELEGH		0x313
385 #define CSR_MIEH		0x314
386 #define CSR_MVIENH		0x318
387 #define CSR_MVIPH		0x319
388 #define CSR_MIPH		0x354
389 
390 #define CSR_VSTART		0x8
391 #define CSR_VCSR		0xf
392 #define CSR_VL			0xc20
393 #define CSR_VTYPE		0xc21
394 #define CSR_VLENB		0xc22
395 
396 #ifdef CONFIG_RISCV_M_MODE
397 # define CSR_STATUS	CSR_MSTATUS
398 # define CSR_IE		CSR_MIE
399 # define CSR_TVEC	CSR_MTVEC
400 # define CSR_SCRATCH	CSR_MSCRATCH
401 # define CSR_EPC	CSR_MEPC
402 # define CSR_CAUSE	CSR_MCAUSE
403 # define CSR_TVAL	CSR_MTVAL
404 # define CSR_IP		CSR_MIP
405 
406 # define CSR_IEH		CSR_MIEH
407 # define CSR_ISELECT	CSR_MISELECT
408 # define CSR_IREG	CSR_MIREG
409 # define CSR_IPH		CSR_MIPH
410 # define CSR_TOPEI	CSR_MTOPEI
411 # define CSR_TOPI	CSR_MTOPI
412 
413 # define SR_IE		SR_MIE
414 # define SR_PIE		SR_MPIE
415 # define SR_PP		SR_MPP
416 
417 # define RV_IRQ_SOFT		IRQ_M_SOFT
418 # define RV_IRQ_TIMER	IRQ_M_TIMER
419 # define RV_IRQ_EXT		IRQ_M_EXT
420 #else /* CONFIG_RISCV_M_MODE */
421 # define CSR_STATUS	CSR_SSTATUS
422 # define CSR_IE		CSR_SIE
423 # define CSR_TVEC	CSR_STVEC
424 # define CSR_SCRATCH	CSR_SSCRATCH
425 # define CSR_EPC	CSR_SEPC
426 # define CSR_CAUSE	CSR_SCAUSE
427 # define CSR_TVAL	CSR_STVAL
428 # define CSR_IP		CSR_SIP
429 
430 # define CSR_IEH		CSR_SIEH
431 # define CSR_ISELECT	CSR_SISELECT
432 # define CSR_IREG	CSR_SIREG
433 # define CSR_IPH		CSR_SIPH
434 # define CSR_TOPEI	CSR_STOPEI
435 # define CSR_TOPI	CSR_STOPI
436 
437 # define SR_IE		SR_SIE
438 # define SR_PIE		SR_SPIE
439 # define SR_PP		SR_SPP
440 
441 # define RV_IRQ_SOFT		IRQ_S_SOFT
442 # define RV_IRQ_TIMER	IRQ_S_TIMER
443 # define RV_IRQ_EXT		IRQ_S_EXT
444 # define RV_IRQ_PMU	IRQ_PMU_OVF
445 # define SIP_LCOFIP     (_AC(0x1, UL) << IRQ_PMU_OVF)
446 
447 #endif /* !CONFIG_RISCV_M_MODE */
448 
449 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
450 #define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
451 #define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
452 #define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
453 
454 #ifndef __ASSEMBLY__
455 
456 #define csr_swap(csr, val)					\
457 ({								\
458 	unsigned long __v = (unsigned long)(val);		\
459 	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
460 			      : "=r" (__v) : "rK" (__v)		\
461 			      : "memory");			\
462 	__v;							\
463 })
464 
465 #define csr_read(csr)						\
466 ({								\
467 	register unsigned long __v;				\
468 	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
469 			      : "=r" (__v) :			\
470 			      : "memory");			\
471 	__v;							\
472 })
473 
474 #define csr_write(csr, val)					\
475 ({								\
476 	unsigned long __v = (unsigned long)(val);		\
477 	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
478 			      : : "rK" (__v)			\
479 			      : "memory");			\
480 })
481 
482 #define csr_read_set(csr, val)					\
483 ({								\
484 	unsigned long __v = (unsigned long)(val);		\
485 	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
486 			      : "=r" (__v) : "rK" (__v)		\
487 			      : "memory");			\
488 	__v;							\
489 })
490 
491 #define csr_set(csr, val)					\
492 ({								\
493 	unsigned long __v = (unsigned long)(val);		\
494 	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
495 			      : : "rK" (__v)			\
496 			      : "memory");			\
497 })
498 
499 #define csr_read_clear(csr, val)				\
500 ({								\
501 	unsigned long __v = (unsigned long)(val);		\
502 	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
503 			      : "=r" (__v) : "rK" (__v)		\
504 			      : "memory");			\
505 	__v;							\
506 })
507 
508 #define csr_clear(csr, val)					\
509 ({								\
510 	unsigned long __v = (unsigned long)(val);		\
511 	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
512 			      : : "rK" (__v)			\
513 			      : "memory");			\
514 })
515 
516 #endif /* __ASSEMBLY__ */
517 
518 #endif /* _ASM_RISCV_CSR_H */
519