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Searched refs:ENABLE_L2_FRAGMENT_PROCESSING (Results 1 – 25 of 30) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/radeon/
Drv770.c907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
954 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_disable()
984 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
Drv770d.h644 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) macro
Dnid.h106 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) macro
Dsid.h371 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) macro
Dcikd.h489 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) macro
Dr600.c1142 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1196 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable()
1234 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
Devergreen.c2412 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2466 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2495 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
Dgfxhub_v2_0.c216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v2_0_init_cache_regs()
Dgfxhub_v3_0_3.c223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v3_0_3_init_cache_regs()
Dgfxhub_v3_0.c218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v3_0_init_cache_regs()
Dmmhub_v3_0_2.c236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in mmhub_v3_0_2_init_cache_regs()
Dmmhub_v3_0_1.c237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in mmhub_v3_0_1_init_cache_regs()
Dmmhub_v2_0.c287 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in mmhub_v2_0_init_cache_regs()
Dmmhub_v2_3.c211 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in mmhub_v2_3_init_cache_regs()
Dmmhub_v3_0.c244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in mmhub_v3_0_init_cache_regs()
Dgfxhub_v1_2.c230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_2_xcc_init_cache_regs()
Dmmhub_v1_0.c167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
Dgfxhub_v2_1.c219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); in gfxhub_v2_1_init_cache_regs()
Dmmhub_v1_8.c230 ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_8_init_cache_regs()
Dgmc_v7_0.c629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
Dmmhub_v1_7.c185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_7_init_cache_regs()
Dgmc_v8_0.c844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
Dsid.h372 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) macro
Dmmhub_v9_4.c211 ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v9_4_init_cache_regs()

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