Searched refs:DP_TRAINING_PATTERN_1 (Results 1 – 16 of 16) sorted by relevance
530 case DP_TRAINING_PATTERN_1: in drm_dp_link_train_wait()626 link->train.pattern = DP_TRAINING_PATTERN_1; in drm_dp_link_clock_recovery()804 link->train.pattern = DP_TRAINING_PATTERN_1; in drm_dp_link_train_fast()
829 case DP_TRAINING_PATTERN_1: in tegra_sor_dp_link_apply_training()
572 case DP_TRAINING_PATTERN_1: in radeon_dp_set_tp()585 case DP_TRAINING_PATTERN_1: in radeon_dp_set_tp()672 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); in radeon_dp_link_train_cr()
522 case DP_TRAINING_PATTERN_1: in amdgpu_atombios_dp_set_tp()605 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); in amdgpu_atombios_dp_link_train_cr()
476 case DP_TRAINING_PATTERN_1: in dp_training_pattern_name()790 DP_TRAINING_PATTERN_1 | in intel_dp_link_training_clock_recovery()1147 DP_TRAINING_PATTERN_1)) { in intel_dp_128b132b_lane_eq()
574 case DP_TRAINING_PATTERN_1: in cpt_set_link_train()602 case DP_TRAINING_PATTERN_1: in g4x_set_link_train()625 DP_PHY_DPRX, DP_TRAINING_PATTERN_1); in intel_dp_enable_port()
3524 case DP_TRAINING_PATTERN_1: in intel_ddi_set_link_train()
687 DP_TRAINING_PATTERN_1); in zynqmp_dp_link_train_cr()689 DP_TRAINING_PATTERN_1 | in zynqmp_dp_link_train_cr()
563 # define DP_TRAINING_PATTERN_1 1 macro
1507 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) { in cdv_intel_dp_start_link_train()1513 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1); in cdv_intel_dp_start_link_train()
312 DP_TRAINING_PATTERN_1); in analogix_dp_link_start()
1110 DP_TRAINING_PATTERN_1); in tc_main_link_enable()
1695 DP_TRAINING_PATTERN_1); in it6505_step_cr_train()
1098 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | in dp_ctrl_link_train_1()
1453 aux_offset = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1; in mtk_dp_pattern()
923 DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE); in cdns_mhdp_link_training_init()