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Searched refs:DPU_IRQ_IDX (Results 1 – 18 of 18) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_8_0_sc8280xp.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
223 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
231 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
239 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
247 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_3_0_msm8998.h47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
188 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
189 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
195 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
196 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
202 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
[all …]
Ddpu_4_0_sdm845.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
212 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
213 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
219 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
220 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
226 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
[all …]
Ddpu_5_1_sc8180x.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
237 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
245 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_6_0_sm8250.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
237 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
245 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_7_0_sm8350.h45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
237 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
245 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_7_2_sc7280.h37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
133 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
141 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
149 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
157 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
183 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
195 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
[all …]
Ddpu_5_0_sm8150.h46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
66 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
71 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
230 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
238 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
246 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_5_4_sm6125.h38 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
63 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
131 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
139 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
152 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
153 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
[all …]
Ddpu_8_1_sm8450.h46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
66 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
71 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
232 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
248 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_9_0_sm8550.h47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
72 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
238 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
246 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
254 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
262 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
Ddpu_6_2_sc7180.h37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
122 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
130 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
143 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
144 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
153 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
154 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
155 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
[all …]
Ddpu_6_4_sm6350.h39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
130 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
138 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
159 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
160 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
169 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
170 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
[all …]
Ddpu_6_5_qcm2290.h33 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
84 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
97 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
98 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
99 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
Ddpu_6_3_sm6115.h34 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
85 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
98 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
99 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
100 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
Ddpu_6_9_sm6375.h35 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
87 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
108 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
109 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
110 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
/linux-6.6.21/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.h39 #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) macro
Ddpu_hw_interrupts.c263 irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1); in dpu_core_irq()