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/linux-6.6.21/Documentation/devicetree/bindings/mips/brcm/ !
Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
/linux-6.6.21/Documentation/driver-api/thermal/ !
Dintel_dptf.rst188 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
209 DRAM devices of DDR IO interface and their power plane can generate EMI
211 mechanism by which DDR data rates can be changed if several conditions
212 are met: there is strong RFI interference because of DDR; CPU power
213 management has no other restriction in changing DDR data rates;
214 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
215 DDR-RFIM) for Wi-Fi from BIOS.
249 Request the restriction of specific DDR data rate and set this
257 Restricted DDR data rate for RFI protection: Lower Limit
260 Restricted DDR data rate for RFI protection: Upper Limit
[all …]
/linux-6.6.21/Documentation/admin-guide/perf/ !
Dmeson-ddr-pmu.rst4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
24 Below are DDR access request event filter keywords:
55 + Show the total DDR bandwidth per seconds:
62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
Dalibaba_pmu.rst9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
44 for connecting an SoC application bus to DDR memory devices. The DDRCTL
49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
/linux-6.6.21/Documentation/ABI/testing/ !
Dsysfs-driver-bd9571mwv-regulator5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
Dsysfs-platform-brcmstb-memc7 internal DDR controller clock cycles. Possible values range
15 DDR PHY frequency in Hz.
/linux-6.6.21/Documentation/devicetree/bindings/clock/ !
Dmvebu-core-clock.txt12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/ !
Dsnps,dw-umctl2-ddrc.yaml14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
27 description: Synopsys DW uMCTL2 DDR controller v3.80a
29 - description: Synopsys DW uMCTL2 DDR controller
31 - description: Xilinx ZynqMP DDR controller v2.40a
Dqca,ath79-ddr-controller.yaml7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
Drockchip,rk3399-dmc.yaml20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
331 frequency in Hz. When the DDR frequency is greater than
[all …]
Dcalxeda-ddr-ctrlr.yaml7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
Dxlnx,zynq-ddrc-a05.yaml7 title: Zynq A05 DDR Memory Controller
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
Drenesas,dbsc.yaml7 title: Renesas DDR Bus Controllers
15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
/linux-6.6.21/drivers/gpio/ !
Dgpio-mb86s7x.c31 #define DDR(x) (0x10 + x / 8 * 4) macro
83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/linux-6.6.21/Documentation/devicetree/bindings/arm/bcm/ !
Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
/linux-6.6.21/drivers/perf/amlogic/ !
DKconfig3 tristate "Amlogic DDR Bandwidth Performance Monitor"
6 Provides support for the DDR performance monitor
/linux-6.6.21/drivers/perf/ !
DKconfig123 tristate "Freescale i.MX8 DDR perf monitor"
126 Provides support for the DDR performance monitor in i.MX8, which
131 tristate "Freescale i.MX9 DDR perf monitor"
134 Provides support for the DDR performance monitor in i.MX9, which
205 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
208 Support for Driveway PMU events monitoring on Yitian 710 DDR
217 Enable perf support for Marvell DDR Performance monitoring
/linux-6.6.21/drivers/mtd/lpddr/ !
DKconfig10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
/linux-6.6.21/arch/arm/mach-omap2/ !
Dsleep24xx.S55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
/linux-6.6.21/Documentation/devicetree/bindings/perf/ !
Damlogic,g12-ddr-pmu.yaml7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
/linux-6.6.21/Documentation/devicetree/bindings/pinctrl/ !
Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
/linux-6.6.21/Documentation/accel/qaic/ !
Daic100.rst17 Each SoC has an A53 management CPU. On card, there can be up to 32 GB of DDR.
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
59 * DDR
98 DDR section in Hardware Description
101 AIC100 has on-card DDR. In total, an AIC100 can have up to 32 GB of DDR.
102 This DDR is used to store workloads, data for the workloads, and is used by the
103 QSM for managing the device. NSPs are granted access to sections of the DDR by
104 the QSM. The host does not have direct access to the DDR, and must make
105 requests to the QSM to transfer data to the DDR.
119 device DDR
[all …]
/linux-6.6.21/Documentation/driver-api/memory-devices/ !
Dti-emif.rst38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/fsl/ !
Dimx8m-ddrc.yaml7 title: i.MX8M DDR Controller
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/ddr/ !
Djedec,lpddr3-timings.yaml19 Maximum DDR clock frequency for the speed-bin, in Hz.
26 Maximum DDR clock frequency for the speed-bin, in Hz.
31 Minimum DDR clock frequency for the speed-bin, in Hz.

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