Home
last modified time | relevance | path

Searched refs:CXL_COMPONENT_REG_BLOCK_SIZE (Results 1 – 5 of 5) sorted by relevance

/linux-6.6.21/drivers/cxl/core/
Dregs.c531 if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE)) in __rcrb_to_component()
Dhdm.c91 .max_size = CXL_COMPONENT_REG_BLOCK_SIZE, in map_hdm_decoder_regs()
167 crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); in devm_cxl_setup_hdm()
Dport.c713 .max_size = CXL_COMPONENT_REG_BLOCK_SIZE, in cxl_setup_comp_regs()
/linux-6.6.21/drivers/cxl/
Dcxl.h22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K macro
Dpci.c494 map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; in cxl_rcrb_get_comp_regs()