Searched refs:CTRL1 (Results 1 – 6 of 6) sorted by relevance
393 .enable_reg = MAX77802_REG_BUCK ## num ## CTRL1, \396 .ramp_reg = MAX77802_REG_BUCK ## num ## CTRL1, \
113 #define CTRL1 0x03 /* Control 1 */ macro642 snd_soc_component_update_bits(component, CTRL1, FMT_MASK, priv->ctrl1); in ak4613_dai_hw_params()
51 #define CTRL1 0x6C /* Control1 register */ macro
440 reg_val = readl(mmio + CTRL1); in amd8111e_restart()442 writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1); in amd8111e_restart()579 writel(CTRL1_DEFAULT, mmio + CTRL1); in amd8111e_init_hw_default()
48 the PMIC must manually set PWRHOLD bit in CTRL1 register to turn off the
96 #define CTRL1 0xC3 /* DSP Module enable 1 */ macro