Searched refs:CSR_CYCLE (Results 1 – 7 of 7) sorted by relevance
61 {.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm },64 {.base = CSR_CYCLE, .count = 31, .func = kvm_riscv_vcpu_pmu_read_hpm },
207 #define CSR_CYCLE 0xc00 macro
400 #define CSR_CYCLE 0xc00 macro437 switchcase_csr_read_32(CSR_CYCLE, ret) in csr_read_num()453 return csr_read_num(CSR_CYCLE + counter); in read_perf_counter()
293 if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) { in kvm_riscv_vcpu_pmu_read_hpm()305 cidx = csr_num - CSR_CYCLE; in kvm_riscv_vcpu_pmu_read_hpm()601 pmc->cinfo.csr = CSR_CYCLE + i; in kvm_riscv_vcpu_pmu_init()
53 val = riscv_pmu_ctr_read_csr(CSR_CYCLE); in pmu_legacy_read_ctr()
118 switchcase_csr_read_32(CSR_CYCLE, ret) in csr_read_num()138 if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H || in riscv_pmu_ctr_read_csr()
302 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) in riscv_pmu_get_hpm_info()317 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; in pmu_sbi_csr_index()364 cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); in pmu_sbi_ctr_get_idx()732 hidx = info->csr - CSR_CYCLE; in pmu_sbi_ovf_handler()