Home
last modified time | relevance | path

Searched refs:CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dsid.h2432 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
Dgfx_v6_0.c3295 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
3300 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()
Dgfx_v7_0.c4767 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()
4772 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2376 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro
Dgfx_7_2_sh_mask.h1179 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
Dgfx_8_0_sh_mask.h1507 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
Dgfx_8_1_sh_mask.h2031 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11005 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_9_1_sh_mask.h12486 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_9_2_1_sh_mask.h12290 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_9_4_3_sh_mask.h14015 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_9_4_2_sh_mask.h2306 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_11_0_0_sh_mask.h15419 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_10_1_0_sh_mask.h17950 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_11_0_3_sh_mask.h17574 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro
Dgc_10_3_0_sh_mask.h16214 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK … macro