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/linux-6.6.21/Documentation/kbuild/
DKconfig.recursion-issue-0113 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
30 # what values are possible for CORE we ended up needing to address questions
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
38 # of the "select CORE" from CORE_BELL_A_ADVANCED as that is implicit already
39 # since CORE_BELL_A depends on CORE. Recursive dependency issues are not always
[all …]
DKconfig.recursion-issue-0225 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
63 select CORE
/linux-6.6.21/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinitvals_init.h87 { MT_BBP(CORE, 1), 0x00000002 },
88 { MT_BBP(CORE, 4), 0x00000000 },
89 { MT_BBP(CORE, 24), 0x00000000 },
90 { MT_BBP(CORE, 32), 0x4003000a },
91 { MT_BBP(CORE, 42), 0x00000000 },
92 { MT_BBP(CORE, 44), 0x00000000 },
Dphy.c191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
518 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
526 mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); in mt76x0_phy_tssi_dc_calibrate()
527 dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
536 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
552 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { in mt76x0_phy_tssi_adc_calibrate()
[all …]
/linux-6.6.21/drivers/net/wireless/mediatek/mt76/mt76x2/
Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
Dusb_mac.c143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
Dpci_phy.c83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
/linux-6.6.21/Documentation/devicetree/bindings/regulator/
Dnvidia,tegra-regulators-coupling.txt11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
/linux-6.6.21/arch/arm/boot/dts/socionext/
Duniphier-pro5-epcore.dts3 * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE)
14 model = "UniPhier Pro5 EP-CORE Board";
/linux-6.6.21/drivers/infiniband/hw/hfi1/
Dchip_registers.h9 #define CORE 0x000000000000 macro
10 #define CCE (CORE + 0x000000000000)
11 #define ASIC (CORE + 0x000000400000)
12 #define MISC (CORE + 0x000000500000)
13 #define DC_TOP_CSRS (CORE + 0x000000600000)
14 #define CHIP_DEBUG (CORE + 0x000000700000)
15 #define RXE (CORE + 0x000001000000)
16 #define TXE (CORE + 0x000001800000)
/linux-6.6.21/drivers/cpufreq/
Dimx-cpufreq-dt.c39 CORE, enumerator
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
/linux-6.6.21/arch/arm/boot/dts/ti/omap/
Domap5-core-thermal.dtsi3 * Device Tree Source for OMAP543x SoC CORE thermal
/linux-6.6.21/drivers/gpu/drm/nouveau/dispnv50/
Dcrcc57d.c18 u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crcc57d_set_src()
Dcrc907d.c31 u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crc907d_set_src()
Dbase907c.c166 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE)); in base907c_csc_clr()
/linux-6.6.21/Documentation/devicetree/bindings/mmc/
Dlitex,mmc.yaml29 - description: CORE registers
/linux-6.6.21/Documentation/devicetree/bindings/mfd/
Dda9052-i2c.txt19 buck1 : regulator BUCK CORE
/linux-6.6.21/tools/perf/tests/attr/
Dtest-stat-default159 # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
Dtest-stat-detailed-1161 # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
Dtest-stat-detailed-2161 # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
Dtest-stat-detailed-3161 # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE
/linux-6.6.21/drivers/regulator/
Dtps68470-regulator.c103 TPS68470_REGULATOR(CORE, TPS68470_CORE, tps68470_regulator_ops, 43,
/linux-6.6.21/drivers/net/wireless/mediatek/mt76/
Dmt76x02_phy.c143 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); in mt76x02_phy_set_bw()
/linux-6.6.21/arch/arm/mach-omap2/
Dsleep34xx.S354 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
374 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
/linux-6.6.21/Documentation/devicetree/bindings/remoteproc/
Dqcom,sdm845-adsp-pil.yaml50 - description: Q6SP6SS CORE clock

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