1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_DSP 0x16
47
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
58
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
61
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
69
70 #define SCP_SET 0
71 #define SCP_GET 1
72
73 #define EFX_FILE "ctefx.bin"
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT,
90 };
91
92 enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95 };
96
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 REAR_MIC,
102 REAR_LINE_IN,
103 FRONT_MIC,
104 };
105
106 enum {
107 #define VNODE_START_NID 0x80
108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
109 VNID_MIC,
110 VNID_HP_SEL,
111 VNID_AMIC1_SEL,
112 VNID_HP_ASEL,
113 VNID_AMIC1_ASEL,
114 VNODE_END_NID,
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
116
117 #define EFFECT_START_NID 0x90
118 #define OUT_EFFECT_START_NID EFFECT_START_NID
119 SURROUND = OUT_EFFECT_START_NID,
120 CRYSTALIZER,
121 DIALOG_PLUS,
122 SMART_VOLUME,
123 X_BASS,
124 EQUALIZER,
125 OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127
128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
129 ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 VOICE_FOCUS,
131 MIC_SVM,
132 NOISE_REDUCTION,
133 IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135
136 VOICEFX = IN_EFFECT_END_NID,
137 PLAY_ENHANCEMENT,
138 CRYSTAL_VOICE,
139 EFFECT_END_NID,
140 OUTPUT_SOURCE_ENUM,
141 INPUT_SOURCE_ENUM,
142 XBASS_XOVER,
143 EQ_PRESET_ENUM,
144 SMART_VOLUME_ENUM,
145 MIC_BOOST_ENUM,
146 AE5_HEADPHONE_GAIN_ENUM,
147 AE5_SOUND_FILTER_ENUM,
148 ZXR_HEADPHONE_GAIN,
149 SPEAKER_CHANNEL_CFG_ENUM,
150 SPEAKER_FULL_RANGE_FRONT,
151 SPEAKER_FULL_RANGE_REAR,
152 BASS_REDIRECTION,
153 BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 };
156
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159
160 /*
161 * Default values for the effect slider controls, they are in order of their
162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 * X-bass.
164 */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY 0
171 #define DSP_CRYSTAL_VOICE_LATENCY 124
172 #define DSP_PLAYBACK_INIT_LATENCY 13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
174 #define DSP_SPEAKER_OUT_LATENCY 7
175
176 struct ct_effect {
177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
178 hda_nid_t nid;
179 int mid; /*effect module ID*/
180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN 1
189
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 { .name = "Surround",
192 .nid = SURROUND,
193 .mid = 0x96,
194 .reqs = {0, 1},
195 .direct = EFX_DIR_OUT,
196 .params = 1,
197 .def_vals = {0x3F800000, 0x3F2B851F}
198 },
199 { .name = "Crystalizer",
200 .nid = CRYSTALIZER,
201 .mid = 0x96,
202 .reqs = {7, 8},
203 .direct = EFX_DIR_OUT,
204 .params = 1,
205 .def_vals = {0x3F800000, 0x3F266666}
206 },
207 { .name = "Dialog Plus",
208 .nid = DIALOG_PLUS,
209 .mid = 0x96,
210 .reqs = {2, 3},
211 .direct = EFX_DIR_OUT,
212 .params = 1,
213 .def_vals = {0x00000000, 0x3F000000}
214 },
215 { .name = "Smart Volume",
216 .nid = SMART_VOLUME,
217 .mid = 0x96,
218 .reqs = {4, 5, 6},
219 .direct = EFX_DIR_OUT,
220 .params = 2,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 },
223 { .name = "X-Bass",
224 .nid = X_BASS,
225 .mid = 0x96,
226 .reqs = {24, 23, 25},
227 .direct = EFX_DIR_OUT,
228 .params = 2,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 },
231 { .name = "Equalizer",
232 .nid = EQUALIZER,
233 .mid = 0x96,
234 .reqs = {9, 10, 11, 12, 13, 14,
235 15, 16, 17, 18, 19, 20},
236 .direct = EFX_DIR_OUT,
237 .params = 11,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 },
242 { .name = "Echo Cancellation",
243 .nid = ECHO_CANCELLATION,
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
246 .direct = EFX_DIR_IN,
247 .params = 3,
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 },
250 { .name = "Voice Focus",
251 .nid = VOICE_FOCUS,
252 .mid = 0x95,
253 .reqs = {6, 7, 8, 9},
254 .direct = EFX_DIR_IN,
255 .params = 3,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 },
258 { .name = "Mic SVM",
259 .nid = MIC_SVM,
260 .mid = 0x95,
261 .reqs = {44, 45},
262 .direct = EFX_DIR_IN,
263 .params = 1,
264 .def_vals = {0x00000000, 0x3F3D70A4}
265 },
266 { .name = "Noise Reduction",
267 .nid = NOISE_REDUCTION,
268 .mid = 0x95,
269 .reqs = {4, 5},
270 .direct = EFX_DIR_IN,
271 .params = 1,
272 .def_vals = {0x3F800000, 0x3F000000}
273 },
274 { .name = "VoiceFX",
275 .nid = VOICEFX,
276 .mid = 0x95,
277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 .direct = EFX_DIR_IN,
279 .params = 8,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
283 }
284 };
285
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288
289 enum {
290 #define TUNING_CTL_START_NID 0xC0
291 WEDGE_ANGLE = TUNING_CTL_START_NID,
292 SVM_LEVEL,
293 EQUALIZER_BAND_0,
294 EQUALIZER_BAND_1,
295 EQUALIZER_BAND_2,
296 EQUALIZER_BAND_3,
297 EQUALIZER_BAND_4,
298 EQUALIZER_BAND_5,
299 EQUALIZER_BAND_6,
300 EQUALIZER_BAND_7,
301 EQUALIZER_BAND_8,
302 EQUALIZER_BAND_9,
303 TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306
307 struct ct_tuning_ctl {
308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
309 hda_nid_t parent_nid;
310 hda_nid_t nid;
311 int mid; /*effect module ID*/
312 int req; /*effect module request*/
313 int direct; /* 0:output; 1:input*/
314 unsigned int def_val;/*effect default values*/
315 };
316
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 { .name = "Wedge Angle",
319 .parent_nid = VOICE_FOCUS,
320 .nid = WEDGE_ANGLE,
321 .mid = 0x95,
322 .req = 8,
323 .direct = EFX_DIR_IN,
324 .def_val = 0x41F00000
325 },
326 { .name = "SVM Level",
327 .parent_nid = MIC_SVM,
328 .nid = SVM_LEVEL,
329 .mid = 0x95,
330 .req = 45,
331 .direct = EFX_DIR_IN,
332 .def_val = 0x3F3D70A4
333 },
334 { .name = "EQ Band0",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_0,
337 .mid = 0x96,
338 .req = 11,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band1",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_1,
345 .mid = 0x96,
346 .req = 12,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band2",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_2,
353 .mid = 0x96,
354 .req = 13,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band3",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_3,
361 .mid = 0x96,
362 .req = 14,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band4",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_4,
369 .mid = 0x96,
370 .req = 15,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band5",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_5,
377 .mid = 0x96,
378 .req = 16,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 },
382 { .name = "EQ Band6",
383 .parent_nid = EQUALIZER,
384 .nid = EQUALIZER_BAND_6,
385 .mid = 0x96,
386 .req = 17,
387 .direct = EFX_DIR_OUT,
388 .def_val = 0x00000000
389 },
390 { .name = "EQ Band7",
391 .parent_nid = EQUALIZER,
392 .nid = EQUALIZER_BAND_7,
393 .mid = 0x96,
394 .req = 18,
395 .direct = EFX_DIR_OUT,
396 .def_val = 0x00000000
397 },
398 { .name = "EQ Band8",
399 .parent_nid = EQUALIZER,
400 .nid = EQUALIZER_BAND_8,
401 .mid = 0x96,
402 .req = 19,
403 .direct = EFX_DIR_OUT,
404 .def_val = 0x00000000
405 },
406 { .name = "EQ Band9",
407 .parent_nid = EQUALIZER,
408 .nid = EQUALIZER_BAND_9,
409 .mid = 0x96,
410 .req = 20,
411 .direct = EFX_DIR_OUT,
412 .def_val = 0x00000000
413 }
414 };
415 #endif
416
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419
420 struct ct_voicefx {
421 char *name;
422 hda_nid_t nid;
423 int mid;
424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426
427 struct ct_voicefx_preset {
428 char *name; /*preset name*/
429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431
432 static const struct ct_voicefx ca0132_voicefx = {
433 .name = "VoiceFX Capture Switch",
434 .nid = VOICEFX,
435 .mid = 0x95,
436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 { .name = "Neutral",
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "Female2Male",
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Male2Female",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "ScrappyKid",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "Elderly",
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 },
465 { .name = "Orc",
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Elf",
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Dwarf",
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "AlienBrute",
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 },
485 { .name = "Robot",
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
489 },
490 { .name = "Marine",
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
494 },
495 { .name = "Emo",
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
499 },
500 { .name = "DeepVoice",
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
504 },
505 { .name = "Munchkin",
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
509 }
510 };
511
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515
516 struct ct_eq {
517 char *name;
518 hda_nid_t nid;
519 int mid;
520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522
523 struct ct_eq_preset {
524 char *name; /*preset name*/
525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 .name = "FX: Equalizer Preset Switch",
530 .nid = EQ_PRESET_ENUM,
531 .mid = 0x96,
532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534
535
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 { .name = "Flat",
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
542 },
543 { .name = "Acoustic",
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
548 },
549 { .name = "Classical",
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
554 },
555 { .name = "Country",
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
560 },
561 { .name = "Dance",
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
566 },
567 { .name = "Jazz",
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
572 },
573 { .name = "New Age",
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
578 },
579 { .name = "Pop",
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
584 },
585 { .name = "Rock",
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
590 },
591 { .name = "Vocal",
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
596 }
597 };
598
599 /*
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601 * set as not being full range, and bass redirection is enabled, all
602 * frequencies below the crossover frequency are redirected to the LFE
603 * channel. If the surround configuration has no LFE channel, this can't be
604 * enabled. X-Bass must be disabled when using these.
605 */
606 enum speaker_range_reqs {
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
615 };
616
617 /*
618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
619 * module ID 0x96, the output effects module.
620 */
621 enum speaker_tuning_reqs {
622 /*
623 * Currently, this value is always set to 0.0f. However, on Windows,
624 * when selecting certain headphone profiles on the new Sound Blaster
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 * sent. This gets the speaker EQ address area, which is then used to
627 * send over (presumably) an equalizer profile for the specific
628 * headphone setup. It is sent using the same method the DSP
629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 * file exists in linux firmware tree but goes unused. It would also
631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 * set to 1.0f.
634 */
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 /*
646 * Inversion is used when setting headphone virtualization to line
647 * out. Not sure why this is, but it's the only place it's ever used.
648 */
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
657 /* Delay is used when setting surround speaker distance in Windows. */
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
666 /* Of these two, only mute seems to ever be used. */
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
669 };
670
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 SPEAKER_CHANNELS_2_0,
675 SPEAKER_CHANNELS_2_1,
676 SPEAKER_CHANNELS_4_0,
677 SPEAKER_CHANNELS_4_1,
678 SPEAKER_CHANNELS_5_1,
679 };
680
681 struct ca0132_alt_speaker_channel_cfg {
682 char *name;
683 unsigned int val;
684 };
685
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 { .name = "2.0",
688 .val = FLOAT_ONE
689 },
690 { .name = "2.1",
691 .val = FLOAT_TWO
692 },
693 { .name = "4.0",
694 .val = FLOAT_FIVE
695 },
696 { .name = "4.1",
697 .val = FLOAT_SIX
698 },
699 { .name = "5.1",
700 .val = FLOAT_EIGHT
701 }
702 };
703
704 /*
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706 * and I don't know what the third req is, but it's always zero. I assume it's
707 * some sort of update or set command to tell the DSP there's new volume info.
708 */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN 1
711
712 struct ct_dsp_volume_ctl {
713 hda_nid_t vnid;
714 int mid; /* module ID*/
715 unsigned int reqs[3]; /* scp req ID */
716 };
717
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 { .vnid = VNID_SPK,
720 .mid = 0x32,
721 .reqs = {3, 4, 2}
722 },
723 { .vnid = VNID_MIC,
724 .mid = 0x37,
725 .reqs = {2, 3, 1}
726 }
727 };
728
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 /* Speakers. */
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 /* Headphones. */
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 /* Speakers. */
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 /* Headphones. */
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 char *name;
759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 },
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 },
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
771 }
772 };
773
774 struct ae5_filter_set {
775 char *name;
776 unsigned int val;
777 };
778
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 { .name = "Slow Roll Off",
781 .val = 0xa0
782 },
783 { .name = "Minimum Phase",
784 .val = 0xc0
785 },
786 { .name = "Fast Roll Off",
787 .val = 0x80
788 }
789 };
790
791 /*
792 * Data structures for storing audio router remapping data. These are used to
793 * remap a currently active streams ports.
794 */
795 struct chipio_stream_remap_data {
796 unsigned int stream_id;
797 unsigned int count;
798
799 unsigned int offset[16];
800 unsigned int value[16];
801 };
802
803 static const struct chipio_stream_remap_data stream_remap_data[] = {
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
808 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
816 },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
822 }
823 };
824
825 enum hda_cmd_vendor_io {
826 /* for DspIO node */
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
829
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
836
837 /* for ChipIO node */
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
843
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
846
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
851
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
857
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
860
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
869
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
874
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
879
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
886
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
888 };
889
890 /*
891 * Control flag IDs
892 */
893 enum control_flag_id {
894 /* Connection manager stream setup is bypassed/enabled */
895 CONTROL_FLAG_C_MGR = 0,
896 /* DSP DMA is bypassed/enabled */
897 CONTROL_FLAG_DMA = 1,
898 /* 8051 'idle' mode is disabled/enabled */
899 CONTROL_FLAG_IDLE_ENABLE = 2,
900 /* Tracker for the SPDIF-in path is bypassed/enabled */
901 CONTROL_FLAG_TRACKER = 3,
902 /* DigitalOut to Spdif2Out connection is disabled/enabled */
903 CONTROL_FLAG_SPDIF2OUT = 4,
904 /* Digital Microphone is disabled/enabled */
905 CONTROL_FLAG_DMIC = 5,
906 /* ADC_B rate is 48 kHz/96 kHz */
907 CONTROL_FLAG_ADC_B_96KHZ = 6,
908 /* ADC_C rate is 48 kHz/96 kHz */
909 CONTROL_FLAG_ADC_C_96KHZ = 7,
910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
911 CONTROL_FLAG_DAC_96KHZ = 8,
912 /* DSP rate is 48 kHz/96 kHz */
913 CONTROL_FLAG_DSP_96KHZ = 9,
914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
917 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
919 CONTROL_FLAG_DECODE_LOOP = 12,
920 /* De-emphasis filter on DAC-1 disabled/enabled */
921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
922 /* De-emphasis filter on DAC-2 disabled/enabled */
923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
924 /* De-emphasis filter on DAC-3 disabled/enabled */
925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
926 /* High-pass filter on ADC_B disabled/enabled */
927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
928 /* High-pass filter on ADC_C disabled/enabled */
929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
930 /* Common mode on Port_A disabled/enabled */
931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
932 /* Common mode on Port_D disabled/enabled */
933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
938 /* ASI rate is 48kHz/96kHz */
939 CONTROL_FLAG_ASI_96KHZ = 22,
940 /* DAC power settings able to control attached ports no/yes */
941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
942 /* Clock Stop OK reporting is disabled/enabled */
943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
944 /* Number of control flags */
945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
946 };
947
948 /*
949 * Control parameter IDs
950 */
951 enum control_param_id {
952 /* 0: None, 1: Mic1In*/
953 CONTROL_PARAM_VIP_SOURCE = 1,
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
955 CONTROL_PARAM_SPDIF1_SOURCE = 2,
956 /* Port A output stage gain setting to use when 16 Ohm output
957 * impedance is selected*/
958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
959 /* Port D output stage gain setting to use when 16 Ohm output
960 * impedance is selected*/
961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
962
963 /*
964 * This control param name was found in the 8051 memory, and makes
965 * sense given the fact the AE-5 uses it and has the ASI flag set.
966 */
967 CONTROL_PARAM_ASI = 23,
968
969 /* Stream Control */
970
971 /* Select stream with the given ID */
972 CONTROL_PARAM_STREAM_ID = 24,
973 /* Source connection point for the selected stream */
974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
975 /* Destination connection point for the selected stream */
976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
977 /* Number of audio channels in the selected stream */
978 CONTROL_PARAM_STREAMS_CHANNELS = 27,
979 /*Enable control for the selected stream */
980 CONTROL_PARAM_STREAM_CONTROL = 28,
981
982 /* Connection Point Control */
983
984 /* Select connection point with the given ID */
985 CONTROL_PARAM_CONN_POINT_ID = 29,
986 /* Connection point sample rate */
987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
988
989 /* Node Control */
990
991 /* Select HDA node with the given ID */
992 CONTROL_PARAM_NODE_ID = 31
993 };
994
995 /*
996 * Dsp Io Status codes
997 */
998 enum hda_vendor_status_dspio {
999 /* Success */
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1001 /* Busy, unable to accept new command, the host must retry */
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1003 /* SCP command queue is full */
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1005 /* SCP response queue is empty */
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1007 };
1008
1009 /*
1010 * Chip Io Status codes
1011 */
1012 enum hda_vendor_status_chipio {
1013 /* Success */
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1015 /* Busy, unable to accept new command, the host must retry */
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1017 };
1018
1019 /*
1020 * CA0132 sample rate
1021 */
1022 enum ca0132_sample_rate {
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1039
1040 SR_COUNT = 0x10,
1041
1042 SR_RATE_UNKNOWN = 0x1F
1043 };
1044
1045 enum dsp_download_state {
1046 DSP_DOWNLOAD_FAILED = -1,
1047 DSP_DOWNLOAD_INIT = 0,
1048 DSP_DOWNLOADING = 1,
1049 DSP_DOWNLOADED = 2
1050 };
1051
1052 /* retrieve parameters from hda format */
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1057
1058 /*
1059 * CA0132 specific
1060 */
1061
1062 struct ca0132_spec {
1063 const struct snd_kcontrol_new *mixers[5];
1064 unsigned int num_mixers;
1065 const struct hda_verb *base_init_verbs;
1066 const struct hda_verb *base_exit_verbs;
1067 const struct hda_verb *chip_init_verbs;
1068 const struct hda_verb *desktop_init_verbs;
1069 struct hda_verb *spec_init_verbs;
1070 struct auto_pin_cfg autocfg;
1071
1072 /* Nodes configurations */
1073 struct hda_multi_out multiout;
1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1076 unsigned int num_outputs;
1077 hda_nid_t input_pins[AUTO_PIN_LAST];
1078 hda_nid_t adcs[AUTO_PIN_LAST];
1079 hda_nid_t dig_out;
1080 hda_nid_t dig_in;
1081 unsigned int num_inputs;
1082 hda_nid_t shared_mic_nid;
1083 hda_nid_t shared_out_nid;
1084 hda_nid_t unsol_tag_hp;
1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1086 hda_nid_t unsol_tag_amic1;
1087
1088 /* chip access */
1089 struct mutex chipio_mutex; /* chip access mutex */
1090 u32 curr_chip_addx;
1091
1092 /* DSP download related */
1093 enum dsp_download_state dsp_state;
1094 unsigned int dsp_stream_id;
1095 unsigned int wait_scp;
1096 unsigned int wait_scp_header;
1097 unsigned int wait_num_data;
1098 unsigned int scp_resp_header;
1099 unsigned int scp_resp_data[4];
1100 unsigned int scp_resp_count;
1101 bool startup_check_entered;
1102 bool dsp_reload;
1103
1104 /* mixer and effects related */
1105 unsigned char dmic_ctl;
1106 int cur_out_type;
1107 int cur_mic_type;
1108 long vnode_lvol[VNODES_COUNT];
1109 long vnode_rvol[VNODES_COUNT];
1110 long vnode_lswitch[VNODES_COUNT];
1111 long vnode_rswitch[VNODES_COUNT];
1112 long effects_switch[EFFECTS_COUNT];
1113 long voicefx_val;
1114 long cur_mic_boost;
1115 /* ca0132_alt control related values */
1116 unsigned char in_enum_val;
1117 unsigned char out_enum_val;
1118 unsigned char channel_cfg_val;
1119 unsigned char speaker_range_val[2];
1120 unsigned char mic_boost_enum_val;
1121 unsigned char smart_volume_setting;
1122 unsigned char bass_redirection_val;
1123 long bass_redirect_xover_freq;
1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1125 long xbass_xover_freq;
1126 long eq_preset_val;
1127 unsigned int tlv[4];
1128 struct hda_vmaster_mute_hook vmaster_mute;
1129 /* AE-5 Control values */
1130 unsigned char ae5_headphone_gain_val;
1131 unsigned char ae5_filter_val;
1132 /* ZxR Control Values */
1133 unsigned char zxr_gain_set;
1134
1135 struct hda_codec *codec;
1136 struct delayed_work unsol_hp_work;
1137 int quirk;
1138
1139 #ifdef ENABLE_TUNING_CONTROLS
1140 long cur_ctl_vals[TUNING_CTLS_COUNT];
1141 #endif
1142 /*
1143 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1144 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1145 * things.
1146 */
1147 bool use_pci_mmio;
1148 void __iomem *mem_base;
1149
1150 /*
1151 * Whether or not to use the alt functions like alt_select_out,
1152 * alt_select_in, etc. Only used on desktop codecs for now, because of
1153 * surround sound support.
1154 */
1155 bool use_alt_functions;
1156
1157 /*
1158 * Whether or not to use alt controls: volume effect sliders, EQ
1159 * presets, smart volume presets, and new control names with FX prefix.
1160 * Renames PlayEnhancement and CrystalVoice too.
1161 */
1162 bool use_alt_controls;
1163 };
1164
1165 /*
1166 * CA0132 quirks table
1167 */
1168 enum {
1169 QUIRK_NONE,
1170 QUIRK_ALIENWARE,
1171 QUIRK_ALIENWARE_M17XR4,
1172 QUIRK_SBZ,
1173 QUIRK_ZXR,
1174 QUIRK_ZXR_DBPRO,
1175 QUIRK_R3DI,
1176 QUIRK_R3D,
1177 QUIRK_AE5,
1178 QUIRK_AE7,
1179 };
1180
1181 #ifdef CONFIG_PCI
1182 #define ca0132_quirk(spec) ((spec)->quirk)
1183 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1184 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1185 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1186 #else
1187 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1188 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1189 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1190 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1191 #endif
1192
1193 static const struct hda_pintbl alienware_pincfgs[] = {
1194 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1195 { 0x0c, 0x411111f0 }, /* N/A */
1196 { 0x0d, 0x411111f0 }, /* N/A */
1197 { 0x0e, 0x411111f0 }, /* N/A */
1198 { 0x0f, 0x0321101f }, /* HP */
1199 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1200 { 0x11, 0x03a11021 }, /* Mic */
1201 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1202 { 0x13, 0x411111f0 }, /* N/A */
1203 { 0x18, 0x411111f0 }, /* N/A */
1204 {}
1205 };
1206
1207 /* Sound Blaster Z pin configs taken from Windows Driver */
1208 static const struct hda_pintbl sbz_pincfgs[] = {
1209 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1210 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1211 { 0x0d, 0x014510f0 }, /* Digital Out */
1212 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1213 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1214 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1215 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1216 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1217 { 0x13, 0x908700f0 }, /* What U Hear In*/
1218 { 0x18, 0x50d000f0 }, /* N/A */
1219 {}
1220 };
1221
1222 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1223 static const struct hda_pintbl zxr_pincfgs[] = {
1224 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1225 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1226 { 0x0d, 0x014510f0 }, /* Digital Out */
1227 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1228 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1229 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1230 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1231 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1232 { 0x13, 0x908700f0 }, /* What U Hear In*/
1233 { 0x18, 0x50d000f0 }, /* N/A */
1234 {}
1235 };
1236
1237 /* Recon3D pin configs taken from Windows Driver */
1238 static const struct hda_pintbl r3d_pincfgs[] = {
1239 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1240 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1241 { 0x0d, 0x014510f0 }, /* Digital Out */
1242 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1243 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1244 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1245 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1246 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1247 { 0x13, 0x908700f0 }, /* What U Hear In*/
1248 { 0x18, 0x50d000f0 }, /* N/A */
1249 {}
1250 };
1251
1252 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1253 static const struct hda_pintbl ae5_pincfgs[] = {
1254 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1255 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1256 { 0x0d, 0x014510f0 }, /* Digital Out */
1257 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1258 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1259 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1260 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1261 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1262 { 0x13, 0x908700f0 }, /* What U Hear In*/
1263 { 0x18, 0x50d000f0 }, /* N/A */
1264 {}
1265 };
1266
1267 /* Recon3D integrated pin configs taken from Windows Driver */
1268 static const struct hda_pintbl r3di_pincfgs[] = {
1269 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1270 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1271 { 0x0d, 0x014510f0 }, /* Digital Out */
1272 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1273 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1274 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1275 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1276 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1277 { 0x13, 0x908700f0 }, /* What U Hear In*/
1278 { 0x18, 0x500000f0 }, /* N/A */
1279 {}
1280 };
1281
1282 static const struct hda_pintbl ae7_pincfgs[] = {
1283 { 0x0b, 0x01017010 },
1284 { 0x0c, 0x014510f0 },
1285 { 0x0d, 0x414510f0 },
1286 { 0x0e, 0x01c520f0 },
1287 { 0x0f, 0x01017114 },
1288 { 0x10, 0x01017011 },
1289 { 0x11, 0x018170ff },
1290 { 0x12, 0x01a170f0 },
1291 { 0x13, 0x908700f0 },
1292 { 0x18, 0x500000f0 },
1293 {}
1294 };
1295
1296 static const struct snd_pci_quirk ca0132_quirks[] = {
1297 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1298 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1301 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1305 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1311 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1313 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1315 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1316 {}
1317 };
1318
1319 /* Output selection quirk info structures. */
1320 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1321 #define MAX_QUIRK_SCP_SET_VALS 2
1322 struct ca0132_alt_out_set_info {
1323 unsigned int dac2port; /* ParamID 0x0d value. */
1324
1325 bool has_hda_gpio;
1326 char hda_gpio_pin;
1327 char hda_gpio_set;
1328
1329 unsigned int mmio_gpio_count;
1330 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1331 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1332
1333 unsigned int scp_cmds_count;
1334 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1335 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1336 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1337
1338 bool has_chipio_write;
1339 unsigned int chipio_write_addr;
1340 unsigned int chipio_write_data;
1341 };
1342
1343 struct ca0132_alt_out_set_quirk_data {
1344 int quirk_id;
1345
1346 bool has_headphone_gain;
1347 bool is_ae_series;
1348
1349 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1350 };
1351
1352 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1353 { .quirk_id = QUIRK_R3DI,
1354 .has_headphone_gain = false,
1355 .is_ae_series = false,
1356 .out_set_info = {
1357 /* Speakers. */
1358 { .dac2port = 0x24,
1359 .has_hda_gpio = true,
1360 .hda_gpio_pin = 2,
1361 .hda_gpio_set = 1,
1362 .mmio_gpio_count = 0,
1363 .scp_cmds_count = 0,
1364 .has_chipio_write = false,
1365 },
1366 /* Headphones. */
1367 { .dac2port = 0x21,
1368 .has_hda_gpio = true,
1369 .hda_gpio_pin = 2,
1370 .hda_gpio_set = 0,
1371 .mmio_gpio_count = 0,
1372 .scp_cmds_count = 0,
1373 .has_chipio_write = false,
1374 } },
1375 },
1376 { .quirk_id = QUIRK_R3D,
1377 .has_headphone_gain = false,
1378 .is_ae_series = false,
1379 .out_set_info = {
1380 /* Speakers. */
1381 { .dac2port = 0x24,
1382 .has_hda_gpio = false,
1383 .mmio_gpio_count = 1,
1384 .mmio_gpio_pin = { 1 },
1385 .mmio_gpio_set = { 1 },
1386 .scp_cmds_count = 0,
1387 .has_chipio_write = false,
1388 },
1389 /* Headphones. */
1390 { .dac2port = 0x21,
1391 .has_hda_gpio = false,
1392 .mmio_gpio_count = 1,
1393 .mmio_gpio_pin = { 1 },
1394 .mmio_gpio_set = { 0 },
1395 .scp_cmds_count = 0,
1396 .has_chipio_write = false,
1397 } },
1398 },
1399 { .quirk_id = QUIRK_SBZ,
1400 .has_headphone_gain = false,
1401 .is_ae_series = false,
1402 .out_set_info = {
1403 /* Speakers. */
1404 { .dac2port = 0x18,
1405 .has_hda_gpio = false,
1406 .mmio_gpio_count = 3,
1407 .mmio_gpio_pin = { 7, 4, 1 },
1408 .mmio_gpio_set = { 0, 1, 1 },
1409 .scp_cmds_count = 0,
1410 .has_chipio_write = false, },
1411 /* Headphones. */
1412 { .dac2port = 0x12,
1413 .has_hda_gpio = false,
1414 .mmio_gpio_count = 3,
1415 .mmio_gpio_pin = { 7, 4, 1 },
1416 .mmio_gpio_set = { 1, 1, 0 },
1417 .scp_cmds_count = 0,
1418 .has_chipio_write = false,
1419 } },
1420 },
1421 { .quirk_id = QUIRK_ZXR,
1422 .has_headphone_gain = true,
1423 .is_ae_series = false,
1424 .out_set_info = {
1425 /* Speakers. */
1426 { .dac2port = 0x24,
1427 .has_hda_gpio = false,
1428 .mmio_gpio_count = 3,
1429 .mmio_gpio_pin = { 2, 3, 5 },
1430 .mmio_gpio_set = { 1, 1, 0 },
1431 .scp_cmds_count = 0,
1432 .has_chipio_write = false,
1433 },
1434 /* Headphones. */
1435 { .dac2port = 0x21,
1436 .has_hda_gpio = false,
1437 .mmio_gpio_count = 3,
1438 .mmio_gpio_pin = { 2, 3, 5 },
1439 .mmio_gpio_set = { 0, 1, 1 },
1440 .scp_cmds_count = 0,
1441 .has_chipio_write = false,
1442 } },
1443 },
1444 { .quirk_id = QUIRK_AE5,
1445 .has_headphone_gain = true,
1446 .is_ae_series = true,
1447 .out_set_info = {
1448 /* Speakers. */
1449 { .dac2port = 0xa4,
1450 .has_hda_gpio = false,
1451 .mmio_gpio_count = 0,
1452 .scp_cmds_count = 2,
1453 .scp_cmd_mid = { 0x96, 0x96 },
1454 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1455 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1456 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1457 .has_chipio_write = true,
1458 .chipio_write_addr = 0x0018b03c,
1459 .chipio_write_data = 0x00000012
1460 },
1461 /* Headphones. */
1462 { .dac2port = 0xa1,
1463 .has_hda_gpio = false,
1464 .mmio_gpio_count = 0,
1465 .scp_cmds_count = 2,
1466 .scp_cmd_mid = { 0x96, 0x96 },
1467 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1468 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1469 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1470 .has_chipio_write = true,
1471 .chipio_write_addr = 0x0018b03c,
1472 .chipio_write_data = 0x00000012
1473 } },
1474 },
1475 { .quirk_id = QUIRK_AE7,
1476 .has_headphone_gain = true,
1477 .is_ae_series = true,
1478 .out_set_info = {
1479 /* Speakers. */
1480 { .dac2port = 0x58,
1481 .has_hda_gpio = false,
1482 .mmio_gpio_count = 1,
1483 .mmio_gpio_pin = { 0 },
1484 .mmio_gpio_set = { 1 },
1485 .scp_cmds_count = 2,
1486 .scp_cmd_mid = { 0x96, 0x96 },
1487 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1488 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1489 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1490 .has_chipio_write = true,
1491 .chipio_write_addr = 0x0018b03c,
1492 .chipio_write_data = 0x00000000
1493 },
1494 /* Headphones. */
1495 { .dac2port = 0x58,
1496 .has_hda_gpio = false,
1497 .mmio_gpio_count = 1,
1498 .mmio_gpio_pin = { 0 },
1499 .mmio_gpio_set = { 1 },
1500 .scp_cmds_count = 2,
1501 .scp_cmd_mid = { 0x96, 0x96 },
1502 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1503 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1504 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1505 .has_chipio_write = true,
1506 .chipio_write_addr = 0x0018b03c,
1507 .chipio_write_data = 0x00000010
1508 } },
1509 }
1510 };
1511
1512 /*
1513 * CA0132 codec access
1514 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1515 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1516 unsigned int verb, unsigned int parm, unsigned int *res)
1517 {
1518 unsigned int response;
1519 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1520 *res = response;
1521
1522 return ((response == -1) ? -1 : 0);
1523 }
1524
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1525 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1526 unsigned short converter_format, unsigned int *res)
1527 {
1528 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1529 converter_format & 0xffff, res);
1530 }
1531
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1532 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1533 hda_nid_t nid, unsigned char stream,
1534 unsigned char channel, unsigned int *res)
1535 {
1536 unsigned char converter_stream_channel = 0;
1537
1538 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1539 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1540 converter_stream_channel, res);
1541 }
1542
1543 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1544 static int chipio_send(struct hda_codec *codec,
1545 unsigned int reg,
1546 unsigned int data)
1547 {
1548 unsigned int res;
1549 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1550
1551 /* send bits of data specified by reg */
1552 do {
1553 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1554 reg, data);
1555 if (res == VENDOR_STATUS_CHIPIO_OK)
1556 return 0;
1557 msleep(20);
1558 } while (time_before(jiffies, timeout));
1559
1560 return -EIO;
1561 }
1562
1563 /*
1564 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1565 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1566 static int chipio_write_address(struct hda_codec *codec,
1567 unsigned int chip_addx)
1568 {
1569 struct ca0132_spec *spec = codec->spec;
1570 int res;
1571
1572 if (spec->curr_chip_addx == chip_addx)
1573 return 0;
1574
1575 /* send low 16 bits of the address */
1576 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1577 chip_addx & 0xffff);
1578
1579 if (res != -EIO) {
1580 /* send high 16 bits of the address */
1581 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1582 chip_addx >> 16);
1583 }
1584
1585 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1586
1587 return res;
1588 }
1589
1590 /*
1591 * Write data through the vendor widget -- NOT protected by the Mutex!
1592 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1593 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1594 {
1595 struct ca0132_spec *spec = codec->spec;
1596 int res;
1597
1598 /* send low 16 bits of the data */
1599 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1600
1601 if (res != -EIO) {
1602 /* send high 16 bits of the data */
1603 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1604 data >> 16);
1605 }
1606
1607 /*If no error encountered, automatically increment the address
1608 as per chip behaviour*/
1609 spec->curr_chip_addx = (res != -EIO) ?
1610 (spec->curr_chip_addx + 4) : ~0U;
1611 return res;
1612 }
1613
1614 /*
1615 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1616 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1617 static int chipio_write_data_multiple(struct hda_codec *codec,
1618 const u32 *data,
1619 unsigned int count)
1620 {
1621 int status = 0;
1622
1623 if (data == NULL) {
1624 codec_dbg(codec, "chipio_write_data null ptr\n");
1625 return -EINVAL;
1626 }
1627
1628 while ((count-- != 0) && (status == 0))
1629 status = chipio_write_data(codec, *data++);
1630
1631 return status;
1632 }
1633
1634
1635 /*
1636 * Read data through the vendor widget -- NOT protected by the Mutex!
1637 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1638 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1639 {
1640 struct ca0132_spec *spec = codec->spec;
1641 int res;
1642
1643 /* post read */
1644 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1645
1646 if (res != -EIO) {
1647 /* read status */
1648 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1649 }
1650
1651 if (res != -EIO) {
1652 /* read data */
1653 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1654 VENDOR_CHIPIO_HIC_READ_DATA,
1655 0);
1656 }
1657
1658 /*If no error encountered, automatically increment the address
1659 as per chip behaviour*/
1660 spec->curr_chip_addx = (res != -EIO) ?
1661 (spec->curr_chip_addx + 4) : ~0U;
1662 return res;
1663 }
1664
1665 /*
1666 * Write given value to the given address through the chip I/O widget.
1667 * protected by the Mutex
1668 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1669 static int chipio_write(struct hda_codec *codec,
1670 unsigned int chip_addx, const unsigned int data)
1671 {
1672 struct ca0132_spec *spec = codec->spec;
1673 int err;
1674
1675 mutex_lock(&spec->chipio_mutex);
1676
1677 /* write the address, and if successful proceed to write data */
1678 err = chipio_write_address(codec, chip_addx);
1679 if (err < 0)
1680 goto exit;
1681
1682 err = chipio_write_data(codec, data);
1683 if (err < 0)
1684 goto exit;
1685
1686 exit:
1687 mutex_unlock(&spec->chipio_mutex);
1688 return err;
1689 }
1690
1691 /*
1692 * Write given value to the given address through the chip I/O widget.
1693 * not protected by the Mutex
1694 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1695 static int chipio_write_no_mutex(struct hda_codec *codec,
1696 unsigned int chip_addx, const unsigned int data)
1697 {
1698 int err;
1699
1700
1701 /* write the address, and if successful proceed to write data */
1702 err = chipio_write_address(codec, chip_addx);
1703 if (err < 0)
1704 goto exit;
1705
1706 err = chipio_write_data(codec, data);
1707 if (err < 0)
1708 goto exit;
1709
1710 exit:
1711 return err;
1712 }
1713
1714 /*
1715 * Write multiple values to the given address through the chip I/O widget.
1716 * protected by the Mutex
1717 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1718 static int chipio_write_multiple(struct hda_codec *codec,
1719 u32 chip_addx,
1720 const u32 *data,
1721 unsigned int count)
1722 {
1723 struct ca0132_spec *spec = codec->spec;
1724 int status;
1725
1726 mutex_lock(&spec->chipio_mutex);
1727 status = chipio_write_address(codec, chip_addx);
1728 if (status < 0)
1729 goto error;
1730
1731 status = chipio_write_data_multiple(codec, data, count);
1732 error:
1733 mutex_unlock(&spec->chipio_mutex);
1734
1735 return status;
1736 }
1737
1738 /*
1739 * Read the given address through the chip I/O widget
1740 * protected by the Mutex
1741 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1742 static int chipio_read(struct hda_codec *codec,
1743 unsigned int chip_addx, unsigned int *data)
1744 {
1745 struct ca0132_spec *spec = codec->spec;
1746 int err;
1747
1748 mutex_lock(&spec->chipio_mutex);
1749
1750 /* write the address, and if successful proceed to write data */
1751 err = chipio_write_address(codec, chip_addx);
1752 if (err < 0)
1753 goto exit;
1754
1755 err = chipio_read_data(codec, data);
1756 if (err < 0)
1757 goto exit;
1758
1759 exit:
1760 mutex_unlock(&spec->chipio_mutex);
1761 return err;
1762 }
1763
1764 /*
1765 * Set chip control flags through the chip I/O widget.
1766 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1767 static void chipio_set_control_flag(struct hda_codec *codec,
1768 enum control_flag_id flag_id,
1769 bool flag_state)
1770 {
1771 unsigned int val;
1772 unsigned int flag_bit;
1773
1774 flag_bit = (flag_state ? 1 : 0);
1775 val = (flag_bit << 7) | (flag_id);
1776 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1777 VENDOR_CHIPIO_FLAG_SET, val);
1778 }
1779
1780 /*
1781 * Set chip parameters through the chip I/O widget.
1782 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1783 static void chipio_set_control_param(struct hda_codec *codec,
1784 enum control_param_id param_id, int param_val)
1785 {
1786 struct ca0132_spec *spec = codec->spec;
1787 int val;
1788
1789 if ((param_id < 32) && (param_val < 8)) {
1790 val = (param_val << 5) | (param_id);
1791 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1792 VENDOR_CHIPIO_PARAM_SET, val);
1793 } else {
1794 mutex_lock(&spec->chipio_mutex);
1795 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1796 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1797 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1798 param_id);
1799 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1800 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1801 param_val);
1802 }
1803 mutex_unlock(&spec->chipio_mutex);
1804 }
1805 }
1806
1807 /*
1808 * Set chip parameters through the chip I/O widget. NO MUTEX.
1809 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1810 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1811 enum control_param_id param_id, int param_val)
1812 {
1813 int val;
1814
1815 if ((param_id < 32) && (param_val < 8)) {
1816 val = (param_val << 5) | (param_id);
1817 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1818 VENDOR_CHIPIO_PARAM_SET, val);
1819 } else {
1820 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1821 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1822 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1823 param_id);
1824 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1825 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1826 param_val);
1827 }
1828 }
1829 }
1830 /*
1831 * Connect stream to a source point, and then connect
1832 * that source point to a destination point.
1833 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1834 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1835 int streamid, int source_point, int dest_point)
1836 {
1837 chipio_set_control_param_no_mutex(codec,
1838 CONTROL_PARAM_STREAM_ID, streamid);
1839 chipio_set_control_param_no_mutex(codec,
1840 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1841 chipio_set_control_param_no_mutex(codec,
1842 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1843 }
1844
1845 /*
1846 * Set number of channels in the selected stream.
1847 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1848 static void chipio_set_stream_channels(struct hda_codec *codec,
1849 int streamid, unsigned int channels)
1850 {
1851 chipio_set_control_param_no_mutex(codec,
1852 CONTROL_PARAM_STREAM_ID, streamid);
1853 chipio_set_control_param_no_mutex(codec,
1854 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1855 }
1856
1857 /*
1858 * Enable/Disable audio stream.
1859 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1860 static void chipio_set_stream_control(struct hda_codec *codec,
1861 int streamid, int enable)
1862 {
1863 chipio_set_control_param_no_mutex(codec,
1864 CONTROL_PARAM_STREAM_ID, streamid);
1865 chipio_set_control_param_no_mutex(codec,
1866 CONTROL_PARAM_STREAM_CONTROL, enable);
1867 }
1868
1869 /*
1870 * Get ChipIO audio stream's status.
1871 */
chipio_get_stream_control(struct hda_codec * codec,int streamid,unsigned int * enable)1872 static void chipio_get_stream_control(struct hda_codec *codec,
1873 int streamid, unsigned int *enable)
1874 {
1875 chipio_set_control_param_no_mutex(codec,
1876 CONTROL_PARAM_STREAM_ID, streamid);
1877 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1878 VENDOR_CHIPIO_PARAM_GET,
1879 CONTROL_PARAM_STREAM_CONTROL);
1880 }
1881
1882 /*
1883 * Set sampling rate of the connection point. NO MUTEX.
1884 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1885 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1886 int connid, enum ca0132_sample_rate rate)
1887 {
1888 chipio_set_control_param_no_mutex(codec,
1889 CONTROL_PARAM_CONN_POINT_ID, connid);
1890 chipio_set_control_param_no_mutex(codec,
1891 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1892 }
1893
1894 /*
1895 * Set sampling rate of the connection point.
1896 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1897 static void chipio_set_conn_rate(struct hda_codec *codec,
1898 int connid, enum ca0132_sample_rate rate)
1899 {
1900 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1901 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1902 rate);
1903 }
1904
1905 /*
1906 * Writes to the 8051's internal address space directly instead of indirectly,
1907 * giving access to the special function registers located at addresses
1908 * 0x80-0xFF.
1909 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1910 static void chipio_8051_write_direct(struct hda_codec *codec,
1911 unsigned int addr, unsigned int data)
1912 {
1913 unsigned int verb;
1914
1915 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1917 }
1918
1919 /*
1920 * Writes to the 8051's exram, which has 16-bits of address space.
1921 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1922 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1923 * setting the pmem bank selection SFR.
1924 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1925 * being writable.
1926 */
chipio_8051_set_address(struct hda_codec * codec,unsigned int addr)1927 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1928 {
1929 unsigned int tmp;
1930
1931 /* Lower 8-bits. */
1932 tmp = addr & 0xff;
1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1934 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1935
1936 /* Upper 8-bits. */
1937 tmp = (addr >> 8) & 0xff;
1938 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1939 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1940 }
1941
chipio_8051_set_data(struct hda_codec * codec,unsigned int data)1942 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1943 {
1944 /* 8-bits of data. */
1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1946 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1947 }
1948
chipio_8051_get_data(struct hda_codec * codec)1949 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1950 {
1951 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1952 VENDOR_CHIPIO_8051_DATA_READ, 0);
1953 }
1954
1955 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
chipio_8051_set_data_pll(struct hda_codec * codec,unsigned int data)1956 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1957 {
1958 /* 8-bits of data. */
1959 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1961 }
1962
chipio_8051_write_exram(struct hda_codec * codec,unsigned int addr,unsigned int data)1963 static void chipio_8051_write_exram(struct hda_codec *codec,
1964 unsigned int addr, unsigned int data)
1965 {
1966 struct ca0132_spec *spec = codec->spec;
1967
1968 mutex_lock(&spec->chipio_mutex);
1969
1970 chipio_8051_set_address(codec, addr);
1971 chipio_8051_set_data(codec, data);
1972
1973 mutex_unlock(&spec->chipio_mutex);
1974 }
1975
chipio_8051_write_exram_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)1976 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1977 unsigned int addr, unsigned int data)
1978 {
1979 chipio_8051_set_address(codec, addr);
1980 chipio_8051_set_data(codec, data);
1981 }
1982
1983 /* Readback data from the 8051's exram. No mutex. */
chipio_8051_read_exram(struct hda_codec * codec,unsigned int addr,unsigned int * data)1984 static void chipio_8051_read_exram(struct hda_codec *codec,
1985 unsigned int addr, unsigned int *data)
1986 {
1987 chipio_8051_set_address(codec, addr);
1988 *data = chipio_8051_get_data(codec);
1989 }
1990
chipio_8051_write_pll_pmu(struct hda_codec * codec,unsigned int addr,unsigned int data)1991 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1992 unsigned int addr, unsigned int data)
1993 {
1994 struct ca0132_spec *spec = codec->spec;
1995
1996 mutex_lock(&spec->chipio_mutex);
1997
1998 chipio_8051_set_address(codec, addr & 0xff);
1999 chipio_8051_set_data_pll(codec, data);
2000
2001 mutex_unlock(&spec->chipio_mutex);
2002 }
2003
chipio_8051_write_pll_pmu_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)2004 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2005 unsigned int addr, unsigned int data)
2006 {
2007 chipio_8051_set_address(codec, addr & 0xff);
2008 chipio_8051_set_data_pll(codec, data);
2009 }
2010
2011 /*
2012 * Enable clocks.
2013 */
chipio_enable_clocks(struct hda_codec * codec)2014 static void chipio_enable_clocks(struct hda_codec *codec)
2015 {
2016 struct ca0132_spec *spec = codec->spec;
2017
2018 mutex_lock(&spec->chipio_mutex);
2019
2020 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2021 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2022 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2023
2024 mutex_unlock(&spec->chipio_mutex);
2025 }
2026
2027 /*
2028 * CA0132 DSP IO stuffs
2029 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)2030 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2031 unsigned int data)
2032 {
2033 int res;
2034 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2035
2036 /* send bits of data specified by reg to dsp */
2037 do {
2038 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2039 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2040 return res;
2041 msleep(20);
2042 } while (time_before(jiffies, timeout));
2043
2044 return -EIO;
2045 }
2046
2047 /*
2048 * Wait for DSP to be ready for commands
2049 */
dspio_write_wait(struct hda_codec * codec)2050 static void dspio_write_wait(struct hda_codec *codec)
2051 {
2052 int status;
2053 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2054
2055 do {
2056 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2057 VENDOR_DSPIO_STATUS, 0);
2058 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2059 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2060 break;
2061 msleep(1);
2062 } while (time_before(jiffies, timeout));
2063 }
2064
2065 /*
2066 * Write SCP data to DSP
2067 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)2068 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2069 {
2070 struct ca0132_spec *spec = codec->spec;
2071 int status;
2072
2073 dspio_write_wait(codec);
2074
2075 mutex_lock(&spec->chipio_mutex);
2076 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2077 scp_data & 0xffff);
2078 if (status < 0)
2079 goto error;
2080
2081 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2082 scp_data >> 16);
2083 if (status < 0)
2084 goto error;
2085
2086 /* OK, now check if the write itself has executed*/
2087 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2088 VENDOR_DSPIO_STATUS, 0);
2089 error:
2090 mutex_unlock(&spec->chipio_mutex);
2091
2092 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2093 -EIO : 0;
2094 }
2095
2096 /*
2097 * Write multiple SCP data to DSP
2098 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)2099 static int dspio_write_multiple(struct hda_codec *codec,
2100 unsigned int *buffer, unsigned int size)
2101 {
2102 int status = 0;
2103 unsigned int count;
2104
2105 if (buffer == NULL)
2106 return -EINVAL;
2107
2108 count = 0;
2109 while (count < size) {
2110 status = dspio_write(codec, *buffer++);
2111 if (status != 0)
2112 break;
2113 count++;
2114 }
2115
2116 return status;
2117 }
2118
dspio_read(struct hda_codec * codec,unsigned int * data)2119 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2120 {
2121 int status;
2122
2123 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2124 if (status == -EIO)
2125 return status;
2126
2127 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2128 if (status == -EIO ||
2129 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2130 return -EIO;
2131
2132 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2133 VENDOR_DSPIO_SCP_READ_DATA, 0);
2134
2135 return 0;
2136 }
2137
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)2138 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2139 unsigned int *buf_size, unsigned int size_count)
2140 {
2141 int status = 0;
2142 unsigned int size = *buf_size;
2143 unsigned int count;
2144 unsigned int skip_count;
2145 unsigned int dummy;
2146
2147 if (buffer == NULL)
2148 return -1;
2149
2150 count = 0;
2151 while (count < size && count < size_count) {
2152 status = dspio_read(codec, buffer++);
2153 if (status != 0)
2154 break;
2155 count++;
2156 }
2157
2158 skip_count = count;
2159 if (status == 0) {
2160 while (skip_count < size) {
2161 status = dspio_read(codec, &dummy);
2162 if (status != 0)
2163 break;
2164 skip_count++;
2165 }
2166 }
2167 *buf_size = count;
2168
2169 return status;
2170 }
2171
2172 /*
2173 * Construct the SCP header using corresponding fields
2174 */
2175 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)2176 make_scp_header(unsigned int target_id, unsigned int source_id,
2177 unsigned int get_flag, unsigned int req,
2178 unsigned int device_flag, unsigned int resp_flag,
2179 unsigned int error_flag, unsigned int data_size)
2180 {
2181 unsigned int header = 0;
2182
2183 header = (data_size & 0x1f) << 27;
2184 header |= (error_flag & 0x01) << 26;
2185 header |= (resp_flag & 0x01) << 25;
2186 header |= (device_flag & 0x01) << 24;
2187 header |= (req & 0x7f) << 17;
2188 header |= (get_flag & 0x01) << 16;
2189 header |= (source_id & 0xff) << 8;
2190 header |= target_id & 0xff;
2191
2192 return header;
2193 }
2194
2195 /*
2196 * Extract corresponding fields from SCP header
2197 */
2198 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)2199 extract_scp_header(unsigned int header,
2200 unsigned int *target_id, unsigned int *source_id,
2201 unsigned int *get_flag, unsigned int *req,
2202 unsigned int *device_flag, unsigned int *resp_flag,
2203 unsigned int *error_flag, unsigned int *data_size)
2204 {
2205 if (data_size)
2206 *data_size = (header >> 27) & 0x1f;
2207 if (error_flag)
2208 *error_flag = (header >> 26) & 0x01;
2209 if (resp_flag)
2210 *resp_flag = (header >> 25) & 0x01;
2211 if (device_flag)
2212 *device_flag = (header >> 24) & 0x01;
2213 if (req)
2214 *req = (header >> 17) & 0x7f;
2215 if (get_flag)
2216 *get_flag = (header >> 16) & 0x01;
2217 if (source_id)
2218 *source_id = (header >> 8) & 0xff;
2219 if (target_id)
2220 *target_id = header & 0xff;
2221 }
2222
2223 #define SCP_MAX_DATA_WORDS (16)
2224
2225 /* Structure to contain any SCP message */
2226 struct scp_msg {
2227 unsigned int hdr;
2228 unsigned int data[SCP_MAX_DATA_WORDS];
2229 };
2230
dspio_clear_response_queue(struct hda_codec * codec)2231 static void dspio_clear_response_queue(struct hda_codec *codec)
2232 {
2233 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2234 unsigned int dummy = 0;
2235 int status;
2236
2237 /* clear all from the response queue */
2238 do {
2239 status = dspio_read(codec, &dummy);
2240 } while (status == 0 && time_before(jiffies, timeout));
2241 }
2242
dspio_get_response_data(struct hda_codec * codec)2243 static int dspio_get_response_data(struct hda_codec *codec)
2244 {
2245 struct ca0132_spec *spec = codec->spec;
2246 unsigned int data = 0;
2247 unsigned int count;
2248
2249 if (dspio_read(codec, &data) < 0)
2250 return -EIO;
2251
2252 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2253 spec->scp_resp_header = data;
2254 spec->scp_resp_count = data >> 27;
2255 count = spec->wait_num_data;
2256 dspio_read_multiple(codec, spec->scp_resp_data,
2257 &spec->scp_resp_count, count);
2258 return 0;
2259 }
2260
2261 return -EIO;
2262 }
2263
2264 /*
2265 * Send SCP message to DSP
2266 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)2267 static int dspio_send_scp_message(struct hda_codec *codec,
2268 unsigned char *send_buf,
2269 unsigned int send_buf_size,
2270 unsigned char *return_buf,
2271 unsigned int return_buf_size,
2272 unsigned int *bytes_returned)
2273 {
2274 struct ca0132_spec *spec = codec->spec;
2275 int status;
2276 unsigned int scp_send_size = 0;
2277 unsigned int total_size;
2278 bool waiting_for_resp = false;
2279 unsigned int header;
2280 struct scp_msg *ret_msg;
2281 unsigned int resp_src_id, resp_target_id;
2282 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2283
2284 if (bytes_returned)
2285 *bytes_returned = 0;
2286
2287 /* get scp header from buffer */
2288 header = *((unsigned int *)send_buf);
2289 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2290 &device_flag, NULL, NULL, &data_size);
2291 scp_send_size = data_size + 1;
2292 total_size = (scp_send_size * 4);
2293
2294 if (send_buf_size < total_size)
2295 return -EINVAL;
2296
2297 if (get_flag || device_flag) {
2298 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2299 return -EINVAL;
2300
2301 spec->wait_scp_header = *((unsigned int *)send_buf);
2302
2303 /* swap source id with target id */
2304 resp_target_id = src_id;
2305 resp_src_id = target_id;
2306 spec->wait_scp_header &= 0xffff0000;
2307 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2308 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2309 spec->wait_scp = 1;
2310 waiting_for_resp = true;
2311 }
2312
2313 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2314 scp_send_size);
2315 if (status < 0) {
2316 spec->wait_scp = 0;
2317 return status;
2318 }
2319
2320 if (waiting_for_resp) {
2321 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2322 memset(return_buf, 0, return_buf_size);
2323 do {
2324 msleep(20);
2325 } while (spec->wait_scp && time_before(jiffies, timeout));
2326 waiting_for_resp = false;
2327 if (!spec->wait_scp) {
2328 ret_msg = (struct scp_msg *)return_buf;
2329 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2330 memcpy(&ret_msg->data, spec->scp_resp_data,
2331 spec->wait_num_data);
2332 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2333 status = 0;
2334 } else {
2335 status = -EIO;
2336 }
2337 spec->wait_scp = 0;
2338 }
2339
2340 return status;
2341 }
2342
2343 /**
2344 * dspio_scp - Prepare and send the SCP message to DSP
2345 * @codec: the HDA codec
2346 * @mod_id: ID of the DSP module to send the command
2347 * @src_id: ID of the source
2348 * @req: ID of request to send to the DSP module
2349 * @dir: SET or GET
2350 * @data: pointer to the data to send with the request, request specific
2351 * @len: length of the data, in bytes
2352 * @reply: point to the buffer to hold data returned for a reply
2353 * @reply_len: length of the reply buffer returned from GET
2354 *
2355 * Returns zero or a negative error code.
2356 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)2357 static int dspio_scp(struct hda_codec *codec,
2358 int mod_id, int src_id, int req, int dir, const void *data,
2359 unsigned int len, void *reply, unsigned int *reply_len)
2360 {
2361 int status = 0;
2362 struct scp_msg scp_send, scp_reply;
2363 unsigned int ret_bytes, send_size, ret_size;
2364 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2365 unsigned int reply_data_size;
2366
2367 memset(&scp_send, 0, sizeof(scp_send));
2368 memset(&scp_reply, 0, sizeof(scp_reply));
2369
2370 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2371 return -EINVAL;
2372
2373 if (dir == SCP_GET && reply == NULL) {
2374 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2375 return -EINVAL;
2376 }
2377
2378 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2379 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2380 return -EINVAL;
2381 }
2382
2383 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2384 0, 0, 0, len/sizeof(unsigned int));
2385 if (data != NULL && len > 0) {
2386 len = min((unsigned int)(sizeof(scp_send.data)), len);
2387 memcpy(scp_send.data, data, len);
2388 }
2389
2390 ret_bytes = 0;
2391 send_size = sizeof(unsigned int) + len;
2392 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2393 send_size, (unsigned char *)&scp_reply,
2394 sizeof(scp_reply), &ret_bytes);
2395
2396 if (status < 0) {
2397 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2398 return status;
2399 }
2400
2401 /* extract send and reply headers members */
2402 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2403 NULL, NULL, NULL, NULL, NULL);
2404 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2405 &reply_resp_flag, &reply_error_flag,
2406 &reply_data_size);
2407
2408 if (!send_get_flag)
2409 return 0;
2410
2411 if (reply_resp_flag && !reply_error_flag) {
2412 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2413 / sizeof(unsigned int);
2414
2415 if (*reply_len < ret_size*sizeof(unsigned int)) {
2416 codec_dbg(codec, "reply too long for buf\n");
2417 return -EINVAL;
2418 } else if (ret_size != reply_data_size) {
2419 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2420 return -EINVAL;
2421 } else if (!reply) {
2422 codec_dbg(codec, "NULL reply\n");
2423 return -EINVAL;
2424 } else {
2425 *reply_len = ret_size*sizeof(unsigned int);
2426 memcpy(reply, scp_reply.data, *reply_len);
2427 }
2428 } else {
2429 codec_dbg(codec, "reply ill-formed or errflag set\n");
2430 return -EIO;
2431 }
2432
2433 return status;
2434 }
2435
2436 /*
2437 * Set DSP parameters
2438 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2439 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2440 int src_id, int req, const void *data, unsigned int len)
2441 {
2442 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2443 NULL);
2444 }
2445
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2446 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2447 int req, const unsigned int data)
2448 {
2449 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2450 sizeof(unsigned int));
2451 }
2452
2453 /*
2454 * Allocate a DSP DMA channel via an SCP message
2455 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2456 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2457 {
2458 int status = 0;
2459 unsigned int size = sizeof(*dma_chan);
2460
2461 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2462 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2463 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2464 dma_chan, &size);
2465
2466 if (status < 0) {
2467 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2468 return status;
2469 }
2470
2471 if ((*dma_chan + 1) == 0) {
2472 codec_dbg(codec, "no free dma channels to allocate\n");
2473 return -EBUSY;
2474 }
2475
2476 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2477 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2478
2479 return status;
2480 }
2481
2482 /*
2483 * Free a DSP DMA via an SCP message
2484 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2485 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2486 {
2487 int status = 0;
2488 unsigned int dummy = 0;
2489
2490 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2491 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2492
2493 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2494 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2495 sizeof(dma_chan), NULL, &dummy);
2496
2497 if (status < 0) {
2498 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2499 return status;
2500 }
2501
2502 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2503
2504 return status;
2505 }
2506
2507 /*
2508 * (Re)start the DSP
2509 */
dsp_set_run_state(struct hda_codec * codec)2510 static int dsp_set_run_state(struct hda_codec *codec)
2511 {
2512 unsigned int dbg_ctrl_reg;
2513 unsigned int halt_state;
2514 int err;
2515
2516 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2517 if (err < 0)
2518 return err;
2519
2520 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2521 DSP_DBGCNTL_STATE_LOBIT;
2522
2523 if (halt_state != 0) {
2524 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2525 DSP_DBGCNTL_SS_MASK);
2526 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2527 dbg_ctrl_reg);
2528 if (err < 0)
2529 return err;
2530
2531 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2532 DSP_DBGCNTL_EXEC_MASK;
2533 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2534 dbg_ctrl_reg);
2535 if (err < 0)
2536 return err;
2537 }
2538
2539 return 0;
2540 }
2541
2542 /*
2543 * Reset the DSP
2544 */
dsp_reset(struct hda_codec * codec)2545 static int dsp_reset(struct hda_codec *codec)
2546 {
2547 unsigned int res;
2548 int retry = 20;
2549
2550 codec_dbg(codec, "dsp_reset\n");
2551 do {
2552 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2553 retry--;
2554 } while (res == -EIO && retry);
2555
2556 if (!retry) {
2557 codec_dbg(codec, "dsp_reset timeout\n");
2558 return -EIO;
2559 }
2560
2561 return 0;
2562 }
2563
2564 /*
2565 * Convert chip address to DSP address
2566 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2567 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2568 bool *code, bool *yram)
2569 {
2570 *code = *yram = false;
2571
2572 if (UC_RANGE(chip_addx, 1)) {
2573 *code = true;
2574 return UC_OFF(chip_addx);
2575 } else if (X_RANGE_ALL(chip_addx, 1)) {
2576 return X_OFF(chip_addx);
2577 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2578 *yram = true;
2579 return Y_OFF(chip_addx);
2580 }
2581
2582 return INVALID_CHIP_ADDRESS;
2583 }
2584
2585 /*
2586 * Check if the DSP DMA is active
2587 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2588 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2589 {
2590 unsigned int dma_chnlstart_reg;
2591
2592 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2593
2594 return ((dma_chnlstart_reg & (1 <<
2595 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2596 }
2597
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2598 static int dsp_dma_setup_common(struct hda_codec *codec,
2599 unsigned int chip_addx,
2600 unsigned int dma_chan,
2601 unsigned int port_map_mask,
2602 bool ovly)
2603 {
2604 int status = 0;
2605 unsigned int chnl_prop;
2606 unsigned int dsp_addx;
2607 unsigned int active;
2608 bool code, yram;
2609
2610 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2611
2612 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2613 codec_dbg(codec, "dma chan num invalid\n");
2614 return -EINVAL;
2615 }
2616
2617 if (dsp_is_dma_active(codec, dma_chan)) {
2618 codec_dbg(codec, "dma already active\n");
2619 return -EBUSY;
2620 }
2621
2622 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2623
2624 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2625 codec_dbg(codec, "invalid chip addr\n");
2626 return -ENXIO;
2627 }
2628
2629 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2630 active = 0;
2631
2632 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2633
2634 if (ovly) {
2635 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2636 &chnl_prop);
2637
2638 if (status < 0) {
2639 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2640 return status;
2641 }
2642 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2643 }
2644
2645 if (!code)
2646 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2647 else
2648 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2649
2650 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2651
2652 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2653 if (status < 0) {
2654 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2655 return status;
2656 }
2657 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2658
2659 if (ovly) {
2660 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2661 &active);
2662
2663 if (status < 0) {
2664 codec_dbg(codec, "read ACTIVE Reg fail\n");
2665 return status;
2666 }
2667 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2668 }
2669
2670 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2671 DSPDMAC_ACTIVE_AAR_MASK;
2672
2673 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2674 if (status < 0) {
2675 codec_dbg(codec, "write ACTIVE Reg fail\n");
2676 return status;
2677 }
2678
2679 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2680
2681 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2682 port_map_mask);
2683 if (status < 0) {
2684 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2685 return status;
2686 }
2687 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2688
2689 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2690 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2691 if (status < 0) {
2692 codec_dbg(codec, "write IRQCNT Reg fail\n");
2693 return status;
2694 }
2695 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2696
2697 codec_dbg(codec,
2698 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2699 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2700 chip_addx, dsp_addx, dma_chan,
2701 port_map_mask, chnl_prop, active);
2702
2703 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2704
2705 return 0;
2706 }
2707
2708 /*
2709 * Setup the DSP DMA per-transfer-specific registers
2710 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2711 static int dsp_dma_setup(struct hda_codec *codec,
2712 unsigned int chip_addx,
2713 unsigned int count,
2714 unsigned int dma_chan)
2715 {
2716 int status = 0;
2717 bool code, yram;
2718 unsigned int dsp_addx;
2719 unsigned int addr_field;
2720 unsigned int incr_field;
2721 unsigned int base_cnt;
2722 unsigned int cur_cnt;
2723 unsigned int dma_cfg = 0;
2724 unsigned int adr_ofs = 0;
2725 unsigned int xfr_cnt = 0;
2726 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2727 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2728
2729 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2730
2731 if (count > max_dma_count) {
2732 codec_dbg(codec, "count too big\n");
2733 return -EINVAL;
2734 }
2735
2736 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2737 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2738 codec_dbg(codec, "invalid chip addr\n");
2739 return -ENXIO;
2740 }
2741
2742 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2743
2744 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2745 incr_field = 0;
2746
2747 if (!code) {
2748 addr_field <<= 1;
2749 if (yram)
2750 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2751
2752 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2753 }
2754
2755 dma_cfg = addr_field + incr_field;
2756 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2757 dma_cfg);
2758 if (status < 0) {
2759 codec_dbg(codec, "write DMACFG Reg fail\n");
2760 return status;
2761 }
2762 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2763
2764 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2765 (code ? 0 : 1));
2766
2767 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2768 adr_ofs);
2769 if (status < 0) {
2770 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2771 return status;
2772 }
2773 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2774
2775 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2776
2777 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2778
2779 xfr_cnt = base_cnt | cur_cnt;
2780
2781 status = chipio_write(codec,
2782 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2783 if (status < 0) {
2784 codec_dbg(codec, "write XFRCNT Reg fail\n");
2785 return status;
2786 }
2787 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2788
2789 codec_dbg(codec,
2790 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2791 "ADROFS=0x%x, XFRCNT=0x%x\n",
2792 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2793
2794 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2795
2796 return 0;
2797 }
2798
2799 /*
2800 * Start the DSP DMA
2801 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2802 static int dsp_dma_start(struct hda_codec *codec,
2803 unsigned int dma_chan, bool ovly)
2804 {
2805 unsigned int reg = 0;
2806 int status = 0;
2807
2808 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2809
2810 if (ovly) {
2811 status = chipio_read(codec,
2812 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2813
2814 if (status < 0) {
2815 codec_dbg(codec, "read CHNLSTART reg fail\n");
2816 return status;
2817 }
2818 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2819
2820 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2821 DSPDMAC_CHNLSTART_DIS_MASK);
2822 }
2823
2824 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2825 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2826 if (status < 0) {
2827 codec_dbg(codec, "write CHNLSTART reg fail\n");
2828 return status;
2829 }
2830 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2831
2832 return status;
2833 }
2834
2835 /*
2836 * Stop the DSP DMA
2837 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2838 static int dsp_dma_stop(struct hda_codec *codec,
2839 unsigned int dma_chan, bool ovly)
2840 {
2841 unsigned int reg = 0;
2842 int status = 0;
2843
2844 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2845
2846 if (ovly) {
2847 status = chipio_read(codec,
2848 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2849
2850 if (status < 0) {
2851 codec_dbg(codec, "read CHNLSTART reg fail\n");
2852 return status;
2853 }
2854 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2855 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2856 DSPDMAC_CHNLSTART_DIS_MASK);
2857 }
2858
2859 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2860 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2861 if (status < 0) {
2862 codec_dbg(codec, "write CHNLSTART reg fail\n");
2863 return status;
2864 }
2865 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2866
2867 return status;
2868 }
2869
2870 /**
2871 * dsp_allocate_router_ports - Allocate router ports
2872 *
2873 * @codec: the HDA codec
2874 * @num_chans: number of channels in the stream
2875 * @ports_per_channel: number of ports per channel
2876 * @start_device: start device
2877 * @port_map: pointer to the port list to hold the allocated ports
2878 *
2879 * Returns zero or a negative error code.
2880 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2881 static int dsp_allocate_router_ports(struct hda_codec *codec,
2882 unsigned int num_chans,
2883 unsigned int ports_per_channel,
2884 unsigned int start_device,
2885 unsigned int *port_map)
2886 {
2887 int status = 0;
2888 int res;
2889 u8 val;
2890
2891 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2892 if (status < 0)
2893 return status;
2894
2895 val = start_device << 6;
2896 val |= (ports_per_channel - 1) << 4;
2897 val |= num_chans - 1;
2898
2899 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2900 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2901 val);
2902
2903 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2904 VENDOR_CHIPIO_PORT_ALLOC_SET,
2905 MEM_CONNID_DSP);
2906
2907 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2908 if (status < 0)
2909 return status;
2910
2911 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2912 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2913
2914 *port_map = res;
2915
2916 return (res < 0) ? res : 0;
2917 }
2918
2919 /*
2920 * Free router ports
2921 */
dsp_free_router_ports(struct hda_codec * codec)2922 static int dsp_free_router_ports(struct hda_codec *codec)
2923 {
2924 int status = 0;
2925
2926 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2927 if (status < 0)
2928 return status;
2929
2930 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2931 VENDOR_CHIPIO_PORT_FREE_SET,
2932 MEM_CONNID_DSP);
2933
2934 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2935
2936 return status;
2937 }
2938
2939 /*
2940 * Allocate DSP ports for the download stream
2941 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2942 static int dsp_allocate_ports(struct hda_codec *codec,
2943 unsigned int num_chans,
2944 unsigned int rate_multi, unsigned int *port_map)
2945 {
2946 int status;
2947
2948 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2949
2950 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2951 codec_dbg(codec, "bad rate multiple\n");
2952 return -EINVAL;
2953 }
2954
2955 status = dsp_allocate_router_ports(codec, num_chans,
2956 rate_multi, 0, port_map);
2957
2958 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2959
2960 return status;
2961 }
2962
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2963 static int dsp_allocate_ports_format(struct hda_codec *codec,
2964 const unsigned short fmt,
2965 unsigned int *port_map)
2966 {
2967 unsigned int num_chans;
2968
2969 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2970 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2971 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2972
2973 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2974 codec_dbg(codec, "bad rate multiple\n");
2975 return -EINVAL;
2976 }
2977
2978 num_chans = get_hdafmt_chs(fmt) + 1;
2979
2980 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2981 }
2982
2983 /*
2984 * free DSP ports
2985 */
dsp_free_ports(struct hda_codec * codec)2986 static int dsp_free_ports(struct hda_codec *codec)
2987 {
2988 int status;
2989
2990 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2991
2992 status = dsp_free_router_ports(codec);
2993 if (status < 0) {
2994 codec_dbg(codec, "free router ports fail\n");
2995 return status;
2996 }
2997 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2998
2999 return status;
3000 }
3001
3002 /*
3003 * HDA DMA engine stuffs for DSP code download
3004 */
3005 struct dma_engine {
3006 struct hda_codec *codec;
3007 unsigned short m_converter_format;
3008 struct snd_dma_buffer *dmab;
3009 unsigned int buf_size;
3010 };
3011
3012
3013 enum dma_state {
3014 DMA_STATE_STOP = 0,
3015 DMA_STATE_RUN = 1
3016 };
3017
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)3018 static int dma_convert_to_hda_format(struct hda_codec *codec,
3019 unsigned int sample_rate,
3020 unsigned short channels,
3021 unsigned short *hda_format)
3022 {
3023 unsigned int format_val;
3024
3025 format_val = snd_hdac_calc_stream_format(sample_rate,
3026 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3027
3028 if (hda_format)
3029 *hda_format = (unsigned short)format_val;
3030
3031 return 0;
3032 }
3033
3034 /*
3035 * Reset DMA for DSP download
3036 */
dma_reset(struct dma_engine * dma)3037 static int dma_reset(struct dma_engine *dma)
3038 {
3039 struct hda_codec *codec = dma->codec;
3040 struct ca0132_spec *spec = codec->spec;
3041 int status;
3042
3043 if (dma->dmab->area)
3044 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3045
3046 status = snd_hda_codec_load_dsp_prepare(codec,
3047 dma->m_converter_format,
3048 dma->buf_size,
3049 dma->dmab);
3050 if (status < 0)
3051 return status;
3052 spec->dsp_stream_id = status;
3053 return 0;
3054 }
3055
dma_set_state(struct dma_engine * dma,enum dma_state state)3056 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3057 {
3058 bool cmd;
3059
3060 switch (state) {
3061 case DMA_STATE_STOP:
3062 cmd = false;
3063 break;
3064 case DMA_STATE_RUN:
3065 cmd = true;
3066 break;
3067 default:
3068 return 0;
3069 }
3070
3071 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3072 return 0;
3073 }
3074
dma_get_buffer_size(struct dma_engine * dma)3075 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3076 {
3077 return dma->dmab->bytes;
3078 }
3079
dma_get_buffer_addr(struct dma_engine * dma)3080 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3081 {
3082 return dma->dmab->area;
3083 }
3084
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)3085 static int dma_xfer(struct dma_engine *dma,
3086 const unsigned int *data,
3087 unsigned int count)
3088 {
3089 memcpy(dma->dmab->area, data, count);
3090 return 0;
3091 }
3092
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)3093 static void dma_get_converter_format(
3094 struct dma_engine *dma,
3095 unsigned short *format)
3096 {
3097 if (format)
3098 *format = dma->m_converter_format;
3099 }
3100
dma_get_stream_id(struct dma_engine * dma)3101 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3102 {
3103 struct ca0132_spec *spec = dma->codec->spec;
3104
3105 return spec->dsp_stream_id;
3106 }
3107
3108 struct dsp_image_seg {
3109 u32 magic;
3110 u32 chip_addr;
3111 u32 count;
3112 u32 data[];
3113 };
3114
3115 static const u32 g_magic_value = 0x4c46584d;
3116 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3117
is_valid(const struct dsp_image_seg * p)3118 static bool is_valid(const struct dsp_image_seg *p)
3119 {
3120 return p->magic == g_magic_value;
3121 }
3122
is_hci_prog_list_seg(const struct dsp_image_seg * p)3123 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3124 {
3125 return g_chip_addr_magic_value == p->chip_addr;
3126 }
3127
is_last(const struct dsp_image_seg * p)3128 static bool is_last(const struct dsp_image_seg *p)
3129 {
3130 return p->count == 0;
3131 }
3132
dsp_sizeof(const struct dsp_image_seg * p)3133 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3134 {
3135 return struct_size(p, data, p->count);
3136 }
3137
get_next_seg_ptr(const struct dsp_image_seg * p)3138 static const struct dsp_image_seg *get_next_seg_ptr(
3139 const struct dsp_image_seg *p)
3140 {
3141 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3142 }
3143
3144 /*
3145 * CA0132 chip DSP transfer stuffs. For DSP download.
3146 */
3147 #define INVALID_DMA_CHANNEL (~0U)
3148
3149 /*
3150 * Program a list of address/data pairs via the ChipIO widget.
3151 * The segment data is in the format of successive pairs of words.
3152 * These are repeated as indicated by the segment's count field.
3153 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)3154 static int dspxfr_hci_write(struct hda_codec *codec,
3155 const struct dsp_image_seg *fls)
3156 {
3157 int status;
3158 const u32 *data;
3159 unsigned int count;
3160
3161 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3162 codec_dbg(codec, "hci_write invalid params\n");
3163 return -EINVAL;
3164 }
3165
3166 count = fls->count;
3167 data = (u32 *)(fls->data);
3168 while (count >= 2) {
3169 status = chipio_write(codec, data[0], data[1]);
3170 if (status < 0) {
3171 codec_dbg(codec, "hci_write chipio failed\n");
3172 return status;
3173 }
3174 count -= 2;
3175 data += 2;
3176 }
3177 return 0;
3178 }
3179
3180 /**
3181 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3182 *
3183 * @codec: the HDA codec
3184 * @fls: pointer to a fast load image
3185 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3186 * no relocation
3187 * @dma_engine: pointer to DMA engine to be used for DSP download
3188 * @dma_chan: The number of DMA channels used for DSP download
3189 * @port_map_mask: port mapping
3190 * @ovly: TRUE if overlay format is required
3191 *
3192 * Returns zero or a negative error code.
3193 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)3194 static int dspxfr_one_seg(struct hda_codec *codec,
3195 const struct dsp_image_seg *fls,
3196 unsigned int reloc,
3197 struct dma_engine *dma_engine,
3198 unsigned int dma_chan,
3199 unsigned int port_map_mask,
3200 bool ovly)
3201 {
3202 int status = 0;
3203 bool comm_dma_setup_done = false;
3204 const unsigned int *data;
3205 unsigned int chip_addx;
3206 unsigned int words_to_write;
3207 unsigned int buffer_size_words;
3208 unsigned char *buffer_addx;
3209 unsigned short hda_format;
3210 unsigned int sample_rate_div;
3211 unsigned int sample_rate_mul;
3212 unsigned int num_chans;
3213 unsigned int hda_frame_size_words;
3214 unsigned int remainder_words;
3215 const u32 *data_remainder;
3216 u32 chip_addx_remainder;
3217 unsigned int run_size_words;
3218 const struct dsp_image_seg *hci_write = NULL;
3219 unsigned long timeout;
3220 bool dma_active;
3221
3222 if (fls == NULL)
3223 return -EINVAL;
3224 if (is_hci_prog_list_seg(fls)) {
3225 hci_write = fls;
3226 fls = get_next_seg_ptr(fls);
3227 }
3228
3229 if (hci_write && (!fls || is_last(fls))) {
3230 codec_dbg(codec, "hci_write\n");
3231 return dspxfr_hci_write(codec, hci_write);
3232 }
3233
3234 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3235 codec_dbg(codec, "Invalid Params\n");
3236 return -EINVAL;
3237 }
3238
3239 data = fls->data;
3240 chip_addx = fls->chip_addr;
3241 words_to_write = fls->count;
3242
3243 if (!words_to_write)
3244 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3245 if (reloc)
3246 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3247
3248 if (!UC_RANGE(chip_addx, words_to_write) &&
3249 !X_RANGE_ALL(chip_addx, words_to_write) &&
3250 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3251 codec_dbg(codec, "Invalid chip_addx Params\n");
3252 return -EINVAL;
3253 }
3254
3255 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3256 sizeof(u32);
3257
3258 buffer_addx = dma_get_buffer_addr(dma_engine);
3259
3260 if (buffer_addx == NULL) {
3261 codec_dbg(codec, "dma_engine buffer NULL\n");
3262 return -EINVAL;
3263 }
3264
3265 dma_get_converter_format(dma_engine, &hda_format);
3266 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3267 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3268 num_chans = get_hdafmt_chs(hda_format) + 1;
3269
3270 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3271 (num_chans * sample_rate_mul / sample_rate_div));
3272
3273 if (hda_frame_size_words == 0) {
3274 codec_dbg(codec, "frmsz zero\n");
3275 return -EINVAL;
3276 }
3277
3278 buffer_size_words = min(buffer_size_words,
3279 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3280 65536 : 32768));
3281 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3282 codec_dbg(codec,
3283 "chpadr=0x%08x frmsz=%u nchan=%u "
3284 "rate_mul=%u div=%u bufsz=%u\n",
3285 chip_addx, hda_frame_size_words, num_chans,
3286 sample_rate_mul, sample_rate_div, buffer_size_words);
3287
3288 if (buffer_size_words < hda_frame_size_words) {
3289 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3290 return -EINVAL;
3291 }
3292
3293 remainder_words = words_to_write % hda_frame_size_words;
3294 data_remainder = data;
3295 chip_addx_remainder = chip_addx;
3296
3297 data += remainder_words;
3298 chip_addx += remainder_words*sizeof(u32);
3299 words_to_write -= remainder_words;
3300
3301 while (words_to_write != 0) {
3302 run_size_words = min(buffer_size_words, words_to_write);
3303 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3304 words_to_write, run_size_words, remainder_words);
3305 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3306 if (!comm_dma_setup_done) {
3307 status = dsp_dma_stop(codec, dma_chan, ovly);
3308 if (status < 0)
3309 return status;
3310 status = dsp_dma_setup_common(codec, chip_addx,
3311 dma_chan, port_map_mask, ovly);
3312 if (status < 0)
3313 return status;
3314 comm_dma_setup_done = true;
3315 }
3316
3317 status = dsp_dma_setup(codec, chip_addx,
3318 run_size_words, dma_chan);
3319 if (status < 0)
3320 return status;
3321 status = dsp_dma_start(codec, dma_chan, ovly);
3322 if (status < 0)
3323 return status;
3324 if (!dsp_is_dma_active(codec, dma_chan)) {
3325 codec_dbg(codec, "dspxfr:DMA did not start\n");
3326 return -EIO;
3327 }
3328 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3329 if (status < 0)
3330 return status;
3331 if (remainder_words != 0) {
3332 status = chipio_write_multiple(codec,
3333 chip_addx_remainder,
3334 data_remainder,
3335 remainder_words);
3336 if (status < 0)
3337 return status;
3338 remainder_words = 0;
3339 }
3340 if (hci_write) {
3341 status = dspxfr_hci_write(codec, hci_write);
3342 if (status < 0)
3343 return status;
3344 hci_write = NULL;
3345 }
3346
3347 timeout = jiffies + msecs_to_jiffies(2000);
3348 do {
3349 dma_active = dsp_is_dma_active(codec, dma_chan);
3350 if (!dma_active)
3351 break;
3352 msleep(20);
3353 } while (time_before(jiffies, timeout));
3354 if (dma_active)
3355 break;
3356
3357 codec_dbg(codec, "+++++ DMA complete\n");
3358 dma_set_state(dma_engine, DMA_STATE_STOP);
3359 status = dma_reset(dma_engine);
3360
3361 if (status < 0)
3362 return status;
3363
3364 data += run_size_words;
3365 chip_addx += run_size_words*sizeof(u32);
3366 words_to_write -= run_size_words;
3367 }
3368
3369 if (remainder_words != 0) {
3370 status = chipio_write_multiple(codec, chip_addx_remainder,
3371 data_remainder, remainder_words);
3372 }
3373
3374 return status;
3375 }
3376
3377 /**
3378 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3379 *
3380 * @codec: the HDA codec
3381 * @fls_data: pointer to a fast load image
3382 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3383 * no relocation
3384 * @sample_rate: sampling rate of the stream used for DSP download
3385 * @channels: channels of the stream used for DSP download
3386 * @ovly: TRUE if overlay format is required
3387 *
3388 * Returns zero or a negative error code.
3389 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)3390 static int dspxfr_image(struct hda_codec *codec,
3391 const struct dsp_image_seg *fls_data,
3392 unsigned int reloc,
3393 unsigned int sample_rate,
3394 unsigned short channels,
3395 bool ovly)
3396 {
3397 struct ca0132_spec *spec = codec->spec;
3398 int status;
3399 unsigned short hda_format = 0;
3400 unsigned int response;
3401 unsigned char stream_id = 0;
3402 struct dma_engine *dma_engine;
3403 unsigned int dma_chan;
3404 unsigned int port_map_mask;
3405
3406 if (fls_data == NULL)
3407 return -EINVAL;
3408
3409 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3410 if (!dma_engine)
3411 return -ENOMEM;
3412
3413 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3414 if (!dma_engine->dmab) {
3415 kfree(dma_engine);
3416 return -ENOMEM;
3417 }
3418
3419 dma_engine->codec = codec;
3420 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3421 dma_engine->m_converter_format = hda_format;
3422 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3423 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3424
3425 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3426
3427 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3428 hda_format, &response);
3429
3430 if (status < 0) {
3431 codec_dbg(codec, "set converter format fail\n");
3432 goto exit;
3433 }
3434
3435 status = snd_hda_codec_load_dsp_prepare(codec,
3436 dma_engine->m_converter_format,
3437 dma_engine->buf_size,
3438 dma_engine->dmab);
3439 if (status < 0)
3440 goto exit;
3441 spec->dsp_stream_id = status;
3442
3443 if (ovly) {
3444 status = dspio_alloc_dma_chan(codec, &dma_chan);
3445 if (status < 0) {
3446 codec_dbg(codec, "alloc dmachan fail\n");
3447 dma_chan = INVALID_DMA_CHANNEL;
3448 goto exit;
3449 }
3450 }
3451
3452 port_map_mask = 0;
3453 status = dsp_allocate_ports_format(codec, hda_format,
3454 &port_map_mask);
3455 if (status < 0) {
3456 codec_dbg(codec, "alloc ports fail\n");
3457 goto exit;
3458 }
3459
3460 stream_id = dma_get_stream_id(dma_engine);
3461 status = codec_set_converter_stream_channel(codec,
3462 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3463 if (status < 0) {
3464 codec_dbg(codec, "set stream chan fail\n");
3465 goto exit;
3466 }
3467
3468 while ((fls_data != NULL) && !is_last(fls_data)) {
3469 if (!is_valid(fls_data)) {
3470 codec_dbg(codec, "FLS check fail\n");
3471 status = -EINVAL;
3472 goto exit;
3473 }
3474 status = dspxfr_one_seg(codec, fls_data, reloc,
3475 dma_engine, dma_chan,
3476 port_map_mask, ovly);
3477 if (status < 0)
3478 break;
3479
3480 if (is_hci_prog_list_seg(fls_data))
3481 fls_data = get_next_seg_ptr(fls_data);
3482
3483 if ((fls_data != NULL) && !is_last(fls_data))
3484 fls_data = get_next_seg_ptr(fls_data);
3485 }
3486
3487 if (port_map_mask != 0)
3488 status = dsp_free_ports(codec);
3489
3490 if (status < 0)
3491 goto exit;
3492
3493 status = codec_set_converter_stream_channel(codec,
3494 WIDGET_CHIP_CTRL, 0, 0, &response);
3495
3496 exit:
3497 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3498 dspio_free_dma_chan(codec, dma_chan);
3499
3500 if (dma_engine->dmab->area)
3501 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3502 kfree(dma_engine->dmab);
3503 kfree(dma_engine);
3504
3505 return status;
3506 }
3507
3508 /*
3509 * CA0132 DSP download stuffs.
3510 */
dspload_post_setup(struct hda_codec * codec)3511 static void dspload_post_setup(struct hda_codec *codec)
3512 {
3513 struct ca0132_spec *spec = codec->spec;
3514 codec_dbg(codec, "---- dspload_post_setup ------\n");
3515 if (!ca0132_use_alt_functions(spec)) {
3516 /*set DSP speaker to 2.0 configuration*/
3517 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3518 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3519
3520 /*update write pointer*/
3521 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3522 }
3523 }
3524
3525 /**
3526 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3527 *
3528 * @codec: the HDA codec
3529 * @fls: pointer to a fast load image
3530 * @ovly: TRUE if overlay format is required
3531 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3532 * no relocation
3533 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3534 * @router_chans: number of audio router channels to be allocated (0 means use
3535 * internal defaults; max is 32)
3536 *
3537 * Download DSP from a DSP Image Fast Load structure. This structure is a
3538 * linear, non-constant sized element array of structures, each of which
3539 * contain the count of the data to be loaded, the data itself, and the
3540 * corresponding starting chip address of the starting data location.
3541 * Returns zero or a negative error code.
3542 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3543 static int dspload_image(struct hda_codec *codec,
3544 const struct dsp_image_seg *fls,
3545 bool ovly,
3546 unsigned int reloc,
3547 bool autostart,
3548 int router_chans)
3549 {
3550 int status = 0;
3551 unsigned int sample_rate;
3552 unsigned short channels;
3553
3554 codec_dbg(codec, "---- dspload_image begin ------\n");
3555 if (router_chans == 0) {
3556 if (!ovly)
3557 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3558 else
3559 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3560 }
3561
3562 sample_rate = 48000;
3563 channels = (unsigned short)router_chans;
3564
3565 while (channels > 16) {
3566 sample_rate *= 2;
3567 channels /= 2;
3568 }
3569
3570 do {
3571 codec_dbg(codec, "Ready to program DMA\n");
3572 if (!ovly)
3573 status = dsp_reset(codec);
3574
3575 if (status < 0)
3576 break;
3577
3578 codec_dbg(codec, "dsp_reset() complete\n");
3579 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3580 ovly);
3581
3582 if (status < 0)
3583 break;
3584
3585 codec_dbg(codec, "dspxfr_image() complete\n");
3586 if (autostart && !ovly) {
3587 dspload_post_setup(codec);
3588 status = dsp_set_run_state(codec);
3589 }
3590
3591 codec_dbg(codec, "LOAD FINISHED\n");
3592 } while (0);
3593
3594 return status;
3595 }
3596
3597 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3598 static bool dspload_is_loaded(struct hda_codec *codec)
3599 {
3600 unsigned int data = 0;
3601 int status = 0;
3602
3603 status = chipio_read(codec, 0x40004, &data);
3604 if ((status < 0) || (data != 1))
3605 return false;
3606
3607 return true;
3608 }
3609 #else
3610 #define dspload_is_loaded(codec) false
3611 #endif
3612
dspload_wait_loaded(struct hda_codec * codec)3613 static bool dspload_wait_loaded(struct hda_codec *codec)
3614 {
3615 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3616
3617 do {
3618 if (dspload_is_loaded(codec)) {
3619 codec_info(codec, "ca0132 DSP downloaded and running\n");
3620 return true;
3621 }
3622 msleep(20);
3623 } while (time_before(jiffies, timeout));
3624
3625 codec_err(codec, "ca0132 failed to download DSP\n");
3626 return false;
3627 }
3628
3629 /*
3630 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3631 * based cards, and has a second mmio region, region2, that's used for special
3632 * commands.
3633 */
3634
3635 /*
3636 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3637 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3638 * The first eight bits are just the number of the pin. So far, I've only seen
3639 * this number go to 7.
3640 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3641 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3642 * then off to send that bit.
3643 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3644 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3645 bool enable)
3646 {
3647 struct ca0132_spec *spec = codec->spec;
3648 unsigned short gpio_data;
3649
3650 gpio_data = gpio_pin & 0xF;
3651 gpio_data |= ((enable << 8) & 0x100);
3652
3653 writew(gpio_data, spec->mem_base + 0x320);
3654 }
3655
3656 /*
3657 * Special pci region2 commands that are only used by the AE-5. They follow
3658 * a set format, and require reads at certain points to seemingly 'clear'
3659 * the response data. My first tests didn't do these reads, and would cause
3660 * the card to get locked up until the memory was read. These commands
3661 * seem to work with three distinct values that I've taken to calling group,
3662 * target-id, and value.
3663 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3664 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3665 unsigned int target, unsigned int value)
3666 {
3667 struct ca0132_spec *spec = codec->spec;
3668 unsigned int write_val;
3669
3670 writel(0x0000007e, spec->mem_base + 0x210);
3671 readl(spec->mem_base + 0x210);
3672 writel(0x0000005a, spec->mem_base + 0x210);
3673 readl(spec->mem_base + 0x210);
3674 readl(spec->mem_base + 0x210);
3675
3676 writel(0x00800005, spec->mem_base + 0x20c);
3677 writel(group, spec->mem_base + 0x804);
3678
3679 writel(0x00800005, spec->mem_base + 0x20c);
3680 write_val = (target & 0xff);
3681 write_val |= (value << 8);
3682
3683
3684 writel(write_val, spec->mem_base + 0x204);
3685 /*
3686 * Need delay here or else it goes too fast and works inconsistently.
3687 */
3688 msleep(20);
3689
3690 readl(spec->mem_base + 0x860);
3691 readl(spec->mem_base + 0x854);
3692 readl(spec->mem_base + 0x840);
3693
3694 writel(0x00800004, spec->mem_base + 0x20c);
3695 writel(0x00000000, spec->mem_base + 0x210);
3696 readl(spec->mem_base + 0x210);
3697 readl(spec->mem_base + 0x210);
3698 }
3699
3700 /*
3701 * This second type of command is used for setting the sound filter type.
3702 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3703 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3704 unsigned int group, unsigned int target, unsigned int value)
3705 {
3706 struct ca0132_spec *spec = codec->spec;
3707 unsigned int write_val;
3708
3709 writel(0x0000007e, spec->mem_base + 0x210);
3710 readl(spec->mem_base + 0x210);
3711 writel(0x0000005a, spec->mem_base + 0x210);
3712 readl(spec->mem_base + 0x210);
3713 readl(spec->mem_base + 0x210);
3714
3715 writel(0x00800003, spec->mem_base + 0x20c);
3716 writel(group, spec->mem_base + 0x804);
3717
3718 writel(0x00800005, spec->mem_base + 0x20c);
3719 write_val = (target & 0xff);
3720 write_val |= (value << 8);
3721
3722
3723 writel(write_val, spec->mem_base + 0x204);
3724 msleep(20);
3725 readl(spec->mem_base + 0x860);
3726 readl(spec->mem_base + 0x854);
3727 readl(spec->mem_base + 0x840);
3728
3729 writel(0x00800004, spec->mem_base + 0x20c);
3730 writel(0x00000000, spec->mem_base + 0x210);
3731 readl(spec->mem_base + 0x210);
3732 readl(spec->mem_base + 0x210);
3733 }
3734
3735 /*
3736 * Setup GPIO for the other variants of Core3D.
3737 */
3738
3739 /*
3740 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3741 * the card shows as having no GPIO pins.
3742 */
ca0132_gpio_init(struct hda_codec * codec)3743 static void ca0132_gpio_init(struct hda_codec *codec)
3744 {
3745 struct ca0132_spec *spec = codec->spec;
3746
3747 switch (ca0132_quirk(spec)) {
3748 case QUIRK_SBZ:
3749 case QUIRK_AE5:
3750 case QUIRK_AE7:
3751 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3752 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3753 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3754 break;
3755 case QUIRK_R3DI:
3756 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3757 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3758 break;
3759 default:
3760 break;
3761 }
3762
3763 }
3764
3765 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3766 static void ca0132_gpio_setup(struct hda_codec *codec)
3767 {
3768 struct ca0132_spec *spec = codec->spec;
3769
3770 switch (ca0132_quirk(spec)) {
3771 case QUIRK_SBZ:
3772 snd_hda_codec_write(codec, 0x01, 0,
3773 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3774 snd_hda_codec_write(codec, 0x01, 0,
3775 AC_VERB_SET_GPIO_MASK, 0x07);
3776 snd_hda_codec_write(codec, 0x01, 0,
3777 AC_VERB_SET_GPIO_DATA, 0x04);
3778 snd_hda_codec_write(codec, 0x01, 0,
3779 AC_VERB_SET_GPIO_DATA, 0x06);
3780 break;
3781 case QUIRK_R3DI:
3782 snd_hda_codec_write(codec, 0x01, 0,
3783 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3784 snd_hda_codec_write(codec, 0x01, 0,
3785 AC_VERB_SET_GPIO_MASK, 0x1F);
3786 snd_hda_codec_write(codec, 0x01, 0,
3787 AC_VERB_SET_GPIO_DATA, 0x0C);
3788 break;
3789 default:
3790 break;
3791 }
3792 }
3793
3794 /*
3795 * GPIO control functions for the Recon3D integrated.
3796 */
3797
3798 enum r3di_gpio_bit {
3799 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3800 R3DI_MIC_SELECT_BIT = 1,
3801 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3802 R3DI_OUT_SELECT_BIT = 2,
3803 /*
3804 * I dunno what this actually does, but it stays on until the dsp
3805 * is downloaded.
3806 */
3807 R3DI_GPIO_DSP_DOWNLOADING = 3,
3808 /*
3809 * Same as above, no clue what it does, but it comes on after the dsp
3810 * is downloaded.
3811 */
3812 R3DI_GPIO_DSP_DOWNLOADED = 4
3813 };
3814
3815 enum r3di_mic_select {
3816 /* Set GPIO bit 1 to 0 for rear mic */
3817 R3DI_REAR_MIC = 0,
3818 /* Set GPIO bit 1 to 1 for front microphone*/
3819 R3DI_FRONT_MIC = 1
3820 };
3821
3822 enum r3di_out_select {
3823 /* Set GPIO bit 2 to 0 for headphone */
3824 R3DI_HEADPHONE_OUT = 0,
3825 /* Set GPIO bit 2 to 1 for speaker */
3826 R3DI_LINE_OUT = 1
3827 };
3828 enum r3di_dsp_status {
3829 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3830 R3DI_DSP_DOWNLOADING = 0,
3831 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3832 R3DI_DSP_DOWNLOADED = 1
3833 };
3834
3835
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3836 static void r3di_gpio_mic_set(struct hda_codec *codec,
3837 enum r3di_mic_select cur_mic)
3838 {
3839 unsigned int cur_gpio;
3840
3841 /* Get the current GPIO Data setup */
3842 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3843
3844 switch (cur_mic) {
3845 case R3DI_REAR_MIC:
3846 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3847 break;
3848 case R3DI_FRONT_MIC:
3849 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3850 break;
3851 }
3852 snd_hda_codec_write(codec, codec->core.afg, 0,
3853 AC_VERB_SET_GPIO_DATA, cur_gpio);
3854 }
3855
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3856 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3857 enum r3di_dsp_status dsp_status)
3858 {
3859 unsigned int cur_gpio;
3860
3861 /* Get the current GPIO Data setup */
3862 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3863
3864 switch (dsp_status) {
3865 case R3DI_DSP_DOWNLOADING:
3866 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3867 snd_hda_codec_write(codec, codec->core.afg, 0,
3868 AC_VERB_SET_GPIO_DATA, cur_gpio);
3869 break;
3870 case R3DI_DSP_DOWNLOADED:
3871 /* Set DOWNLOADING bit to 0. */
3872 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3873
3874 snd_hda_codec_write(codec, codec->core.afg, 0,
3875 AC_VERB_SET_GPIO_DATA, cur_gpio);
3876
3877 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3878 break;
3879 }
3880
3881 snd_hda_codec_write(codec, codec->core.afg, 0,
3882 AC_VERB_SET_GPIO_DATA, cur_gpio);
3883 }
3884
3885 /*
3886 * PCM callbacks
3887 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3888 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3889 struct hda_codec *codec,
3890 unsigned int stream_tag,
3891 unsigned int format,
3892 struct snd_pcm_substream *substream)
3893 {
3894 struct ca0132_spec *spec = codec->spec;
3895
3896 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3897
3898 return 0;
3899 }
3900
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3901 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3902 struct hda_codec *codec,
3903 struct snd_pcm_substream *substream)
3904 {
3905 struct ca0132_spec *spec = codec->spec;
3906
3907 if (spec->dsp_state == DSP_DOWNLOADING)
3908 return 0;
3909
3910 /*If Playback effects are on, allow stream some time to flush
3911 *effects tail*/
3912 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3913 msleep(50);
3914
3915 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3916
3917 return 0;
3918 }
3919
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3920 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3921 struct hda_codec *codec,
3922 struct snd_pcm_substream *substream)
3923 {
3924 struct ca0132_spec *spec = codec->spec;
3925 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3926 struct snd_pcm_runtime *runtime = substream->runtime;
3927
3928 if (spec->dsp_state != DSP_DOWNLOADED)
3929 return 0;
3930
3931 /* Add latency if playback enhancement and either effect is enabled. */
3932 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3933 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3934 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3935 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3936 }
3937
3938 /* Applying Speaker EQ adds latency as well. */
3939 if (spec->cur_out_type == SPEAKER_OUT)
3940 latency += DSP_SPEAKER_OUT_LATENCY;
3941
3942 return (latency * runtime->rate) / 1000;
3943 }
3944
3945 /*
3946 * Digital out
3947 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3948 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3949 struct hda_codec *codec,
3950 struct snd_pcm_substream *substream)
3951 {
3952 struct ca0132_spec *spec = codec->spec;
3953 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3954 }
3955
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3956 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3957 struct hda_codec *codec,
3958 unsigned int stream_tag,
3959 unsigned int format,
3960 struct snd_pcm_substream *substream)
3961 {
3962 struct ca0132_spec *spec = codec->spec;
3963 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3964 stream_tag, format, substream);
3965 }
3966
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3967 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3968 struct hda_codec *codec,
3969 struct snd_pcm_substream *substream)
3970 {
3971 struct ca0132_spec *spec = codec->spec;
3972 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3973 }
3974
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3975 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3976 struct hda_codec *codec,
3977 struct snd_pcm_substream *substream)
3978 {
3979 struct ca0132_spec *spec = codec->spec;
3980 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3981 }
3982
3983 /*
3984 * Analog capture
3985 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3986 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3987 struct hda_codec *codec,
3988 unsigned int stream_tag,
3989 unsigned int format,
3990 struct snd_pcm_substream *substream)
3991 {
3992 snd_hda_codec_setup_stream(codec, hinfo->nid,
3993 stream_tag, 0, format);
3994
3995 return 0;
3996 }
3997
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3998 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3999 struct hda_codec *codec,
4000 struct snd_pcm_substream *substream)
4001 {
4002 struct ca0132_spec *spec = codec->spec;
4003
4004 if (spec->dsp_state == DSP_DOWNLOADING)
4005 return 0;
4006
4007 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4008 return 0;
4009 }
4010
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)4011 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4012 struct hda_codec *codec,
4013 struct snd_pcm_substream *substream)
4014 {
4015 struct ca0132_spec *spec = codec->spec;
4016 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4017 struct snd_pcm_runtime *runtime = substream->runtime;
4018
4019 if (spec->dsp_state != DSP_DOWNLOADED)
4020 return 0;
4021
4022 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4023 latency += DSP_CRYSTAL_VOICE_LATENCY;
4024
4025 return (latency * runtime->rate) / 1000;
4026 }
4027
4028 /*
4029 * Controls stuffs.
4030 */
4031
4032 /*
4033 * Mixer controls helpers.
4034 */
4035 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4036 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4037 .name = xname, \
4038 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4039 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4040 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4041 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4042 .info = ca0132_volume_info, \
4043 .get = ca0132_volume_get, \
4044 .put = ca0132_volume_put, \
4045 .tlv = { .c = ca0132_volume_tlv }, \
4046 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4047
4048 /*
4049 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4050 * volume put, which is used for setting the DSP volume. This was done because
4051 * the ca0132 functions were taking too much time and causing lag.
4052 */
4053 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4054 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4055 .name = xname, \
4056 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4057 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4058 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4059 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4060 .info = snd_hda_mixer_amp_volume_info, \
4061 .get = snd_hda_mixer_amp_volume_get, \
4062 .put = ca0132_alt_volume_put, \
4063 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4064 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4065
4066 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4067 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4068 .name = xname, \
4069 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4070 .info = snd_hda_mixer_amp_switch_info, \
4071 .get = ca0132_switch_get, \
4072 .put = ca0132_switch_put, \
4073 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4074
4075 /* stereo */
4076 #define CA0132_CODEC_VOL(xname, nid, dir) \
4077 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4078 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4079 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4080 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4081 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4082
4083 /* lookup tables */
4084 /*
4085 * Lookup table with decibel values for the DSP. When volume is changed in
4086 * Windows, the DSP is also sent the dB value in floating point. In Windows,
4087 * these values have decimal points, probably because the Windows driver
4088 * actually uses floating point. We can't here, so I made a lookup table of
4089 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4090 * DAC's, and 9 is the maximum.
4091 */
4092 static const unsigned int float_vol_db_lookup[] = {
4093 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4094 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4095 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4096 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4097 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4098 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4099 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4100 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4101 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4102 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4103 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4104 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4105 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4106 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4107 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4108 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4109 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4110 };
4111
4112 /*
4113 * This table counts from float 0 to 1 in increments of .01, which is
4114 * useful for a few different sliders.
4115 */
4116 static const unsigned int float_zero_to_one_lookup[] = {
4117 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4118 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4119 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4120 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4121 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4122 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4123 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4124 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4125 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4126 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4127 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4128 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4129 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4130 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4131 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4132 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4133 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4134 };
4135
4136 /*
4137 * This table counts from float 10 to 1000, which is the range of the x-bass
4138 * crossover slider in Windows.
4139 */
4140 static const unsigned int float_xbass_xover_lookup[] = {
4141 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4142 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4143 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4144 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4145 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4146 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4147 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4148 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4149 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4150 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4151 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4152 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4153 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4154 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4155 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4156 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4157 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4158 };
4159
4160 /* The following are for tuning of products */
4161 #ifdef ENABLE_TUNING_CONTROLS
4162
4163 static const unsigned int voice_focus_vals_lookup[] = {
4164 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4165 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4166 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4167 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4168 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4169 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4170 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4171 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4172 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4173 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4174 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4175 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4176 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4177 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4178 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4179 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4180 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4181 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4182 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4183 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4184 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4185 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4186 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4187 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4188 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4189 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4190 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4191 };
4192
4193 static const unsigned int mic_svm_vals_lookup[] = {
4194 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4195 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4196 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4197 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4198 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4199 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4200 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4201 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4202 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4203 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4204 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4205 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4206 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4207 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4208 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4209 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4210 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4211 };
4212
4213 static const unsigned int equalizer_vals_lookup[] = {
4214 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4215 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4216 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4217 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4218 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4219 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4220 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4221 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4222 0x41C00000
4223 };
4224
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)4225 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4226 const unsigned int *lookup, int idx)
4227 {
4228 int i = 0;
4229
4230 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4231 if (nid == ca0132_tuning_ctls[i].nid)
4232 goto found;
4233
4234 return -EINVAL;
4235 found:
4236 snd_hda_power_up(codec);
4237 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4238 ca0132_tuning_ctls[i].req,
4239 &(lookup[idx]), sizeof(unsigned int));
4240 snd_hda_power_down(codec);
4241
4242 return 1;
4243 }
4244
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4245 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4246 struct snd_ctl_elem_value *ucontrol)
4247 {
4248 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4249 struct ca0132_spec *spec = codec->spec;
4250 hda_nid_t nid = get_amp_nid(kcontrol);
4251 long *valp = ucontrol->value.integer.value;
4252 int idx = nid - TUNING_CTL_START_NID;
4253
4254 *valp = spec->cur_ctl_vals[idx];
4255 return 0;
4256 }
4257
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4258 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4259 struct snd_ctl_elem_info *uinfo)
4260 {
4261 int chs = get_amp_channels(kcontrol);
4262 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4263 uinfo->count = chs == 3 ? 2 : 1;
4264 uinfo->value.integer.min = 20;
4265 uinfo->value.integer.max = 180;
4266 uinfo->value.integer.step = 1;
4267
4268 return 0;
4269 }
4270
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4271 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4272 struct snd_ctl_elem_value *ucontrol)
4273 {
4274 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4275 struct ca0132_spec *spec = codec->spec;
4276 hda_nid_t nid = get_amp_nid(kcontrol);
4277 long *valp = ucontrol->value.integer.value;
4278 int idx;
4279
4280 idx = nid - TUNING_CTL_START_NID;
4281 /* any change? */
4282 if (spec->cur_ctl_vals[idx] == *valp)
4283 return 0;
4284
4285 spec->cur_ctl_vals[idx] = *valp;
4286
4287 idx = *valp - 20;
4288 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4289
4290 return 1;
4291 }
4292
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4293 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4294 struct snd_ctl_elem_info *uinfo)
4295 {
4296 int chs = get_amp_channels(kcontrol);
4297 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4298 uinfo->count = chs == 3 ? 2 : 1;
4299 uinfo->value.integer.min = 0;
4300 uinfo->value.integer.max = 100;
4301 uinfo->value.integer.step = 1;
4302
4303 return 0;
4304 }
4305
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4306 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4307 struct snd_ctl_elem_value *ucontrol)
4308 {
4309 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4310 struct ca0132_spec *spec = codec->spec;
4311 hda_nid_t nid = get_amp_nid(kcontrol);
4312 long *valp = ucontrol->value.integer.value;
4313 int idx;
4314
4315 idx = nid - TUNING_CTL_START_NID;
4316 /* any change? */
4317 if (spec->cur_ctl_vals[idx] == *valp)
4318 return 0;
4319
4320 spec->cur_ctl_vals[idx] = *valp;
4321
4322 idx = *valp;
4323 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4324
4325 return 0;
4326 }
4327
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4328 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4329 struct snd_ctl_elem_info *uinfo)
4330 {
4331 int chs = get_amp_channels(kcontrol);
4332 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4333 uinfo->count = chs == 3 ? 2 : 1;
4334 uinfo->value.integer.min = 0;
4335 uinfo->value.integer.max = 48;
4336 uinfo->value.integer.step = 1;
4337
4338 return 0;
4339 }
4340
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4341 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4342 struct snd_ctl_elem_value *ucontrol)
4343 {
4344 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4345 struct ca0132_spec *spec = codec->spec;
4346 hda_nid_t nid = get_amp_nid(kcontrol);
4347 long *valp = ucontrol->value.integer.value;
4348 int idx;
4349
4350 idx = nid - TUNING_CTL_START_NID;
4351 /* any change? */
4352 if (spec->cur_ctl_vals[idx] == *valp)
4353 return 0;
4354
4355 spec->cur_ctl_vals[idx] = *valp;
4356
4357 idx = *valp;
4358 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4359
4360 return 1;
4361 }
4362
4363 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4364 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4365
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)4366 static int add_tuning_control(struct hda_codec *codec,
4367 hda_nid_t pnid, hda_nid_t nid,
4368 const char *name, int dir)
4369 {
4370 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4371 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4372 struct snd_kcontrol_new knew =
4373 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4374
4375 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4376 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4377 knew.tlv.c = 0;
4378 knew.tlv.p = 0;
4379 switch (pnid) {
4380 case VOICE_FOCUS:
4381 knew.info = voice_focus_ctl_info;
4382 knew.get = tuning_ctl_get;
4383 knew.put = voice_focus_ctl_put;
4384 knew.tlv.p = voice_focus_db_scale;
4385 break;
4386 case MIC_SVM:
4387 knew.info = mic_svm_ctl_info;
4388 knew.get = tuning_ctl_get;
4389 knew.put = mic_svm_ctl_put;
4390 break;
4391 case EQUALIZER:
4392 knew.info = equalizer_ctl_info;
4393 knew.get = tuning_ctl_get;
4394 knew.put = equalizer_ctl_put;
4395 knew.tlv.p = eq_db_scale;
4396 break;
4397 default:
4398 return 0;
4399 }
4400 knew.private_value =
4401 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4402 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4403 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4404 }
4405
add_tuning_ctls(struct hda_codec * codec)4406 static int add_tuning_ctls(struct hda_codec *codec)
4407 {
4408 int i;
4409 int err;
4410
4411 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4412 err = add_tuning_control(codec,
4413 ca0132_tuning_ctls[i].parent_nid,
4414 ca0132_tuning_ctls[i].nid,
4415 ca0132_tuning_ctls[i].name,
4416 ca0132_tuning_ctls[i].direct);
4417 if (err < 0)
4418 return err;
4419 }
4420
4421 return 0;
4422 }
4423
ca0132_init_tuning_defaults(struct hda_codec * codec)4424 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4425 {
4426 struct ca0132_spec *spec = codec->spec;
4427 int i;
4428
4429 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4430 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4431 /* SVM level defaults to 0.74. */
4432 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4433
4434 /* EQ defaults to 0dB. */
4435 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4436 spec->cur_ctl_vals[i] = 24;
4437 }
4438 #endif /*ENABLE_TUNING_CONTROLS*/
4439
4440 /*
4441 * Select the active output.
4442 * If autodetect is enabled, output will be selected based on jack detection.
4443 * If jack inserted, headphone will be selected, else built-in speakers
4444 * If autodetect is disabled, output will be selected based on selection.
4445 */
ca0132_select_out(struct hda_codec * codec)4446 static int ca0132_select_out(struct hda_codec *codec)
4447 {
4448 struct ca0132_spec *spec = codec->spec;
4449 unsigned int pin_ctl;
4450 int jack_present;
4451 int auto_jack;
4452 unsigned int tmp;
4453 int err;
4454
4455 codec_dbg(codec, "ca0132_select_out\n");
4456
4457 snd_hda_power_up_pm(codec);
4458
4459 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4460
4461 if (auto_jack)
4462 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4463 else
4464 jack_present =
4465 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4466
4467 if (jack_present)
4468 spec->cur_out_type = HEADPHONE_OUT;
4469 else
4470 spec->cur_out_type = SPEAKER_OUT;
4471
4472 if (spec->cur_out_type == SPEAKER_OUT) {
4473 codec_dbg(codec, "ca0132_select_out speaker\n");
4474 /*speaker out config*/
4475 tmp = FLOAT_ONE;
4476 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4477 if (err < 0)
4478 goto exit;
4479 /*enable speaker EQ*/
4480 tmp = FLOAT_ONE;
4481 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4482 if (err < 0)
4483 goto exit;
4484
4485 /* Setup EAPD */
4486 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4487 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4488 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4489 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4490 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4491 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4492 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4493 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4494
4495 /* disable headphone node */
4496 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4497 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4498 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4499 pin_ctl & ~PIN_HP);
4500 /* enable speaker node */
4501 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4502 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4503 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4504 pin_ctl | PIN_OUT);
4505 } else {
4506 codec_dbg(codec, "ca0132_select_out hp\n");
4507 /*headphone out config*/
4508 tmp = FLOAT_ZERO;
4509 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4510 if (err < 0)
4511 goto exit;
4512 /*disable speaker EQ*/
4513 tmp = FLOAT_ZERO;
4514 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4515 if (err < 0)
4516 goto exit;
4517
4518 /* Setup EAPD */
4519 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4520 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4521 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4522 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4523 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4524 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4525 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4526 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4527
4528 /* disable speaker*/
4529 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4530 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4531 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4532 pin_ctl & ~PIN_HP);
4533 /* enable headphone*/
4534 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4535 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4536 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4537 pin_ctl | PIN_HP);
4538 }
4539
4540 exit:
4541 snd_hda_power_down_pm(codec);
4542
4543 return err < 0 ? err : 0;
4544 }
4545
4546 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4547 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4548 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4549
ae5_mmio_select_out(struct hda_codec * codec)4550 static void ae5_mmio_select_out(struct hda_codec *codec)
4551 {
4552 struct ca0132_spec *spec = codec->spec;
4553 const struct ae_ca0113_output_set *out_cmds;
4554 unsigned int i;
4555
4556 if (ca0132_quirk(spec) == QUIRK_AE5)
4557 out_cmds = &ae5_ca0113_output_presets;
4558 else
4559 out_cmds = &ae7_ca0113_output_presets;
4560
4561 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4562 ca0113_mmio_command_set(codec, out_cmds->group[i],
4563 out_cmds->target[i],
4564 out_cmds->vals[spec->cur_out_type][i]);
4565 }
4566
ca0132_alt_set_full_range_speaker(struct hda_codec * codec)4567 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4568 {
4569 struct ca0132_spec *spec = codec->spec;
4570 int quirk = ca0132_quirk(spec);
4571 unsigned int tmp;
4572 int err;
4573
4574 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4575 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4576 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4577 return 0;
4578
4579 /* Set front L/R full range. Zero for full-range, one for redirection. */
4580 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4581 err = dspio_set_uint_param(codec, 0x96,
4582 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4583 if (err < 0)
4584 return err;
4585
4586 /* When setting full-range rear, both rear and center/lfe are set. */
4587 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4588 err = dspio_set_uint_param(codec, 0x96,
4589 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4590 if (err < 0)
4591 return err;
4592
4593 err = dspio_set_uint_param(codec, 0x96,
4594 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4595 if (err < 0)
4596 return err;
4597
4598 /*
4599 * Only the AE series cards set this value when setting full-range,
4600 * and it's always 1.0f.
4601 */
4602 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4603 err = dspio_set_uint_param(codec, 0x96,
4604 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4605 if (err < 0)
4606 return err;
4607 }
4608
4609 return 0;
4610 }
4611
ca0132_alt_surround_set_bass_redirection(struct hda_codec * codec,bool val)4612 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4613 bool val)
4614 {
4615 struct ca0132_spec *spec = codec->spec;
4616 unsigned int tmp;
4617 int err;
4618
4619 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4620 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4621 tmp = FLOAT_ONE;
4622 else
4623 tmp = FLOAT_ZERO;
4624
4625 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4626 if (err < 0)
4627 return err;
4628
4629 /* If it is enabled, make sure to set the crossover frequency. */
4630 if (tmp) {
4631 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4632 err = dspio_set_uint_param(codec, 0x96,
4633 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4634 if (err < 0)
4635 return err;
4636 }
4637
4638 return 0;
4639 }
4640
4641 /*
4642 * These are the commands needed to setup output on each of the different card
4643 * types.
4644 */
ca0132_alt_select_out_get_quirk_data(struct hda_codec * codec,const struct ca0132_alt_out_set_quirk_data ** quirk_data)4645 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4646 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4647 {
4648 struct ca0132_spec *spec = codec->spec;
4649 int quirk = ca0132_quirk(spec);
4650 unsigned int i;
4651
4652 *quirk_data = NULL;
4653 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4654 if (quirk_out_set_data[i].quirk_id == quirk) {
4655 *quirk_data = &quirk_out_set_data[i];
4656 return;
4657 }
4658 }
4659 }
4660
ca0132_alt_select_out_quirk_set(struct hda_codec * codec)4661 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4662 {
4663 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4664 const struct ca0132_alt_out_set_info *out_info;
4665 struct ca0132_spec *spec = codec->spec;
4666 unsigned int i, gpio_data;
4667 int err;
4668
4669 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4670 if (!quirk_data)
4671 return 0;
4672
4673 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4674 if (quirk_data->is_ae_series)
4675 ae5_mmio_select_out(codec);
4676
4677 if (out_info->has_hda_gpio) {
4678 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4679 AC_VERB_GET_GPIO_DATA, 0);
4680
4681 if (out_info->hda_gpio_set)
4682 gpio_data |= (1 << out_info->hda_gpio_pin);
4683 else
4684 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4685
4686 snd_hda_codec_write(codec, codec->core.afg, 0,
4687 AC_VERB_SET_GPIO_DATA, gpio_data);
4688 }
4689
4690 if (out_info->mmio_gpio_count) {
4691 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4692 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4693 out_info->mmio_gpio_set[i]);
4694 }
4695 }
4696
4697 if (out_info->scp_cmds_count) {
4698 for (i = 0; i < out_info->scp_cmds_count; i++) {
4699 err = dspio_set_uint_param(codec,
4700 out_info->scp_cmd_mid[i],
4701 out_info->scp_cmd_req[i],
4702 out_info->scp_cmd_val[i]);
4703 if (err < 0)
4704 return err;
4705 }
4706 }
4707
4708 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4709
4710 if (out_info->has_chipio_write) {
4711 chipio_write(codec, out_info->chipio_write_addr,
4712 out_info->chipio_write_data);
4713 }
4714
4715 if (quirk_data->has_headphone_gain) {
4716 if (spec->cur_out_type != HEADPHONE_OUT) {
4717 if (quirk_data->is_ae_series)
4718 ae5_headphone_gain_set(codec, 2);
4719 else
4720 zxr_headphone_gain_set(codec, 0);
4721 } else {
4722 if (quirk_data->is_ae_series)
4723 ae5_headphone_gain_set(codec,
4724 spec->ae5_headphone_gain_val);
4725 else
4726 zxr_headphone_gain_set(codec,
4727 spec->zxr_gain_set);
4728 }
4729 }
4730
4731 return 0;
4732 }
4733
ca0132_set_out_node_pincfg(struct hda_codec * codec,hda_nid_t nid,bool out_enable,bool hp_enable)4734 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4735 bool out_enable, bool hp_enable)
4736 {
4737 unsigned int pin_ctl;
4738
4739 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4740 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4741
4742 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4743 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4744 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4745 }
4746
4747 /*
4748 * This function behaves similarly to the ca0132_select_out funciton above,
4749 * except with a few differences. It adds the ability to select the current
4750 * output with an enumerated control "output source" if the auto detect
4751 * mute switch is set to off. If the auto detect mute switch is enabled, it
4752 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4753 * It also adds the ability to auto-detect the front headphone port.
4754 */
ca0132_alt_select_out(struct hda_codec * codec)4755 static int ca0132_alt_select_out(struct hda_codec *codec)
4756 {
4757 struct ca0132_spec *spec = codec->spec;
4758 unsigned int tmp, outfx_set;
4759 int jack_present;
4760 int auto_jack;
4761 int err;
4762 /* Default Headphone is rear headphone */
4763 hda_nid_t headphone_nid = spec->out_pins[1];
4764
4765 codec_dbg(codec, "%s\n", __func__);
4766
4767 snd_hda_power_up_pm(codec);
4768
4769 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4770
4771 /*
4772 * If headphone rear or front is plugged in, set to headphone.
4773 * If neither is plugged in, set to rear line out. Only if
4774 * hp/speaker auto detect is enabled.
4775 */
4776 if (auto_jack) {
4777 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4778 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4779
4780 if (jack_present)
4781 spec->cur_out_type = HEADPHONE_OUT;
4782 else
4783 spec->cur_out_type = SPEAKER_OUT;
4784 } else
4785 spec->cur_out_type = spec->out_enum_val;
4786
4787 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4788
4789 /* Begin DSP output switch, mute DSP volume. */
4790 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4791 if (err < 0)
4792 goto exit;
4793
4794 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4795 goto exit;
4796
4797 switch (spec->cur_out_type) {
4798 case SPEAKER_OUT:
4799 codec_dbg(codec, "%s speaker\n", __func__);
4800
4801 /* Enable EAPD */
4802 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4803 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4804
4805 /* Disable headphone node. */
4806 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4807 /* Set front L-R to output. */
4808 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4809 /* Set Center/LFE to output. */
4810 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4811 /* Set rear surround to output. */
4812 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4813
4814 /*
4815 * Without PlayEnhancement being enabled, if we've got a 2.0
4816 * setup, set it to floating point eight to disable any DSP
4817 * processing effects.
4818 */
4819 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4820 tmp = FLOAT_EIGHT;
4821 else
4822 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4823
4824 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4825 if (err < 0)
4826 goto exit;
4827
4828 break;
4829 case HEADPHONE_OUT:
4830 codec_dbg(codec, "%s hp\n", __func__);
4831 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4832 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4833
4834 /* Disable all speaker nodes. */
4835 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4836 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4837 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4838
4839 /* enable headphone, either front or rear */
4840 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4841 headphone_nid = spec->out_pins[2];
4842 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4843 headphone_nid = spec->out_pins[1];
4844
4845 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4846
4847 if (outfx_set)
4848 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4849 else
4850 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4851
4852 if (err < 0)
4853 goto exit;
4854 break;
4855 }
4856 /*
4857 * If output effects are enabled, set the X-Bass effect value again to
4858 * make sure that it's properly enabled/disabled for speaker
4859 * configurations with an LFE channel.
4860 */
4861 if (outfx_set)
4862 ca0132_effects_set(codec, X_BASS,
4863 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4864
4865 /* Set speaker EQ bypass attenuation to 0. */
4866 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4867 if (err < 0)
4868 goto exit;
4869
4870 /*
4871 * Although unused on all cards but the AE series, this is always set
4872 * to zero when setting the output.
4873 */
4874 err = dspio_set_uint_param(codec, 0x96,
4875 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4876 if (err < 0)
4877 goto exit;
4878
4879 if (spec->cur_out_type == SPEAKER_OUT)
4880 err = ca0132_alt_surround_set_bass_redirection(codec,
4881 spec->bass_redirection_val);
4882 else
4883 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4884
4885 /* Unmute DSP now that we're done with output selection. */
4886 err = dspio_set_uint_param(codec, 0x96,
4887 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4888 if (err < 0)
4889 goto exit;
4890
4891 if (spec->cur_out_type == SPEAKER_OUT) {
4892 err = ca0132_alt_set_full_range_speaker(codec);
4893 if (err < 0)
4894 goto exit;
4895 }
4896
4897 exit:
4898 snd_hda_power_down_pm(codec);
4899
4900 return err < 0 ? err : 0;
4901 }
4902
ca0132_unsol_hp_delayed(struct work_struct * work)4903 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4904 {
4905 struct ca0132_spec *spec = container_of(
4906 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4907 struct hda_jack_tbl *jack;
4908
4909 if (ca0132_use_alt_functions(spec))
4910 ca0132_alt_select_out(spec->codec);
4911 else
4912 ca0132_select_out(spec->codec);
4913
4914 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4915 if (jack) {
4916 jack->block_report = 0;
4917 snd_hda_jack_report_sync(spec->codec);
4918 }
4919 }
4920
4921 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4922 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4923 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4924 static int stop_mic1(struct hda_codec *codec);
4925 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4926 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4927
4928 /*
4929 * Select the active VIP source
4930 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4931 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4932 {
4933 struct ca0132_spec *spec = codec->spec;
4934 unsigned int tmp;
4935
4936 if (spec->dsp_state != DSP_DOWNLOADED)
4937 return 0;
4938
4939 /* if CrystalVoice if off, vipsource should be 0 */
4940 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4941 (val == 0)) {
4942 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4943 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4944 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4945 if (spec->cur_mic_type == DIGITAL_MIC)
4946 tmp = FLOAT_TWO;
4947 else
4948 tmp = FLOAT_ONE;
4949 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4950 tmp = FLOAT_ZERO;
4951 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4952 } else {
4953 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4954 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4955 if (spec->cur_mic_type == DIGITAL_MIC)
4956 tmp = FLOAT_TWO;
4957 else
4958 tmp = FLOAT_ONE;
4959 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4960 tmp = FLOAT_ONE;
4961 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4962 msleep(20);
4963 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4964 }
4965
4966 return 1;
4967 }
4968
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4969 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4970 {
4971 struct ca0132_spec *spec = codec->spec;
4972 unsigned int tmp;
4973
4974 if (spec->dsp_state != DSP_DOWNLOADED)
4975 return 0;
4976
4977 codec_dbg(codec, "%s\n", __func__);
4978
4979 chipio_set_stream_control(codec, 0x03, 0);
4980 chipio_set_stream_control(codec, 0x04, 0);
4981
4982 /* if CrystalVoice is off, vipsource should be 0 */
4983 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4984 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4985 codec_dbg(codec, "%s: off.", __func__);
4986 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4987
4988 tmp = FLOAT_ZERO;
4989 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4990
4991 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4992 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4993 if (ca0132_quirk(spec) == QUIRK_R3DI)
4994 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4995
4996
4997 if (spec->in_enum_val == REAR_LINE_IN)
4998 tmp = FLOAT_ZERO;
4999 else {
5000 if (ca0132_quirk(spec) == QUIRK_SBZ)
5001 tmp = FLOAT_THREE;
5002 else
5003 tmp = FLOAT_ONE;
5004 }
5005
5006 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5007
5008 } else {
5009 codec_dbg(codec, "%s: on.", __func__);
5010 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5011 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5012 if (ca0132_quirk(spec) == QUIRK_R3DI)
5013 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5014
5015 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5016 tmp = FLOAT_TWO;
5017 else
5018 tmp = FLOAT_ONE;
5019 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5020
5021 tmp = FLOAT_ONE;
5022 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5023
5024 msleep(20);
5025 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5026 }
5027
5028 chipio_set_stream_control(codec, 0x03, 1);
5029 chipio_set_stream_control(codec, 0x04, 1);
5030
5031 return 1;
5032 }
5033
5034 /*
5035 * Select the active microphone.
5036 * If autodetect is enabled, mic will be selected based on jack detection.
5037 * If jack inserted, ext.mic will be selected, else built-in mic
5038 * If autodetect is disabled, mic will be selected based on selection.
5039 */
ca0132_select_mic(struct hda_codec * codec)5040 static int ca0132_select_mic(struct hda_codec *codec)
5041 {
5042 struct ca0132_spec *spec = codec->spec;
5043 int jack_present;
5044 int auto_jack;
5045
5046 codec_dbg(codec, "ca0132_select_mic\n");
5047
5048 snd_hda_power_up_pm(codec);
5049
5050 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5051
5052 if (auto_jack)
5053 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5054 else
5055 jack_present =
5056 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5057
5058 if (jack_present)
5059 spec->cur_mic_type = LINE_MIC_IN;
5060 else
5061 spec->cur_mic_type = DIGITAL_MIC;
5062
5063 if (spec->cur_mic_type == DIGITAL_MIC) {
5064 /* enable digital Mic */
5065 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5066 ca0132_set_dmic(codec, 1);
5067 ca0132_mic_boost_set(codec, 0);
5068 /* set voice focus */
5069 ca0132_effects_set(codec, VOICE_FOCUS,
5070 spec->effects_switch
5071 [VOICE_FOCUS - EFFECT_START_NID]);
5072 } else {
5073 /* disable digital Mic */
5074 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5075 ca0132_set_dmic(codec, 0);
5076 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5077 /* disable voice focus */
5078 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5079 }
5080
5081 snd_hda_power_down_pm(codec);
5082
5083 return 0;
5084 }
5085
5086 /*
5087 * Select the active input.
5088 * Mic detection isn't used, because it's kind of pointless on the SBZ.
5089 * The front mic has no jack-detection, so the only way to switch to it
5090 * is to do it manually in alsamixer.
5091 */
ca0132_alt_select_in(struct hda_codec * codec)5092 static int ca0132_alt_select_in(struct hda_codec *codec)
5093 {
5094 struct ca0132_spec *spec = codec->spec;
5095 unsigned int tmp;
5096
5097 codec_dbg(codec, "%s\n", __func__);
5098
5099 snd_hda_power_up_pm(codec);
5100
5101 chipio_set_stream_control(codec, 0x03, 0);
5102 chipio_set_stream_control(codec, 0x04, 0);
5103
5104 spec->cur_mic_type = spec->in_enum_val;
5105
5106 switch (spec->cur_mic_type) {
5107 case REAR_MIC:
5108 switch (ca0132_quirk(spec)) {
5109 case QUIRK_SBZ:
5110 case QUIRK_R3D:
5111 ca0113_mmio_gpio_set(codec, 0, false);
5112 tmp = FLOAT_THREE;
5113 break;
5114 case QUIRK_ZXR:
5115 tmp = FLOAT_THREE;
5116 break;
5117 case QUIRK_R3DI:
5118 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5119 tmp = FLOAT_ONE;
5120 break;
5121 case QUIRK_AE5:
5122 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5123 tmp = FLOAT_THREE;
5124 break;
5125 case QUIRK_AE7:
5126 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5127 tmp = FLOAT_THREE;
5128 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5129 SR_96_000);
5130 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5131 SR_96_000);
5132 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5133 break;
5134 default:
5135 tmp = FLOAT_ONE;
5136 break;
5137 }
5138
5139 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5140 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5141 if (ca0132_quirk(spec) == QUIRK_R3DI)
5142 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5143
5144 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5145
5146 chipio_set_stream_control(codec, 0x03, 1);
5147 chipio_set_stream_control(codec, 0x04, 1);
5148 switch (ca0132_quirk(spec)) {
5149 case QUIRK_SBZ:
5150 chipio_write(codec, 0x18B098, 0x0000000C);
5151 chipio_write(codec, 0x18B09C, 0x0000000C);
5152 break;
5153 case QUIRK_ZXR:
5154 chipio_write(codec, 0x18B098, 0x0000000C);
5155 chipio_write(codec, 0x18B09C, 0x000000CC);
5156 break;
5157 case QUIRK_AE5:
5158 chipio_write(codec, 0x18B098, 0x0000000C);
5159 chipio_write(codec, 0x18B09C, 0x0000004C);
5160 break;
5161 default:
5162 break;
5163 }
5164 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5165 break;
5166 case REAR_LINE_IN:
5167 ca0132_mic_boost_set(codec, 0);
5168 switch (ca0132_quirk(spec)) {
5169 case QUIRK_SBZ:
5170 case QUIRK_R3D:
5171 ca0113_mmio_gpio_set(codec, 0, false);
5172 break;
5173 case QUIRK_R3DI:
5174 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5175 break;
5176 case QUIRK_AE5:
5177 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5178 break;
5179 case QUIRK_AE7:
5180 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5181 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5182 SR_96_000);
5183 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5184 SR_96_000);
5185 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5186 break;
5187 default:
5188 break;
5189 }
5190
5191 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5192 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5193 if (ca0132_quirk(spec) == QUIRK_R3DI)
5194 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5195
5196 if (ca0132_quirk(spec) == QUIRK_AE7)
5197 tmp = FLOAT_THREE;
5198 else
5199 tmp = FLOAT_ZERO;
5200 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5201
5202 switch (ca0132_quirk(spec)) {
5203 case QUIRK_SBZ:
5204 case QUIRK_AE5:
5205 chipio_write(codec, 0x18B098, 0x00000000);
5206 chipio_write(codec, 0x18B09C, 0x00000000);
5207 break;
5208 default:
5209 break;
5210 }
5211 chipio_set_stream_control(codec, 0x03, 1);
5212 chipio_set_stream_control(codec, 0x04, 1);
5213 break;
5214 case FRONT_MIC:
5215 switch (ca0132_quirk(spec)) {
5216 case QUIRK_SBZ:
5217 case QUIRK_R3D:
5218 ca0113_mmio_gpio_set(codec, 0, true);
5219 ca0113_mmio_gpio_set(codec, 5, false);
5220 tmp = FLOAT_THREE;
5221 break;
5222 case QUIRK_R3DI:
5223 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5224 tmp = FLOAT_ONE;
5225 break;
5226 case QUIRK_AE5:
5227 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5228 tmp = FLOAT_THREE;
5229 break;
5230 default:
5231 tmp = FLOAT_ONE;
5232 break;
5233 }
5234
5235 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5236 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5237 if (ca0132_quirk(spec) == QUIRK_R3DI)
5238 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5239
5240 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5241
5242 chipio_set_stream_control(codec, 0x03, 1);
5243 chipio_set_stream_control(codec, 0x04, 1);
5244
5245 switch (ca0132_quirk(spec)) {
5246 case QUIRK_SBZ:
5247 chipio_write(codec, 0x18B098, 0x0000000C);
5248 chipio_write(codec, 0x18B09C, 0x000000CC);
5249 break;
5250 case QUIRK_AE5:
5251 chipio_write(codec, 0x18B098, 0x0000000C);
5252 chipio_write(codec, 0x18B09C, 0x0000004C);
5253 break;
5254 default:
5255 break;
5256 }
5257 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5258 break;
5259 }
5260 ca0132_cvoice_switch_set(codec);
5261
5262 snd_hda_power_down_pm(codec);
5263 return 0;
5264 }
5265
5266 /*
5267 * Check if VNODE settings take effect immediately.
5268 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)5269 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5270 hda_nid_t vnid,
5271 hda_nid_t *shared_nid)
5272 {
5273 struct ca0132_spec *spec = codec->spec;
5274 hda_nid_t nid;
5275
5276 switch (vnid) {
5277 case VNID_SPK:
5278 nid = spec->shared_out_nid;
5279 break;
5280 case VNID_MIC:
5281 nid = spec->shared_mic_nid;
5282 break;
5283 default:
5284 return false;
5285 }
5286
5287 if (shared_nid)
5288 *shared_nid = nid;
5289
5290 return true;
5291 }
5292
5293 /*
5294 * The following functions are control change helpers.
5295 * They return 0 if no changed. Return 1 if changed.
5296 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)5297 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5298 {
5299 struct ca0132_spec *spec = codec->spec;
5300 unsigned int tmp;
5301
5302 /* based on CrystalVoice state to enable VoiceFX. */
5303 if (enable) {
5304 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5305 FLOAT_ONE : FLOAT_ZERO;
5306 } else {
5307 tmp = FLOAT_ZERO;
5308 }
5309
5310 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5311 ca0132_voicefx.reqs[0], tmp);
5312
5313 return 1;
5314 }
5315
5316 /*
5317 * Set the effects parameters
5318 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)5319 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5320 {
5321 struct ca0132_spec *spec = codec->spec;
5322 unsigned int on, tmp, channel_cfg;
5323 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5324 int err = 0;
5325 int idx = nid - EFFECT_START_NID;
5326
5327 if ((idx < 0) || (idx >= num_fx))
5328 return 0; /* no changed */
5329
5330 /* for out effect, qualify with PE */
5331 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5332 /* if PE if off, turn off out effects. */
5333 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5334 val = 0;
5335 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5336 channel_cfg = spec->channel_cfg_val;
5337 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5338 channel_cfg != SPEAKER_CHANNELS_4_0)
5339 val = 0;
5340 }
5341 }
5342
5343 /* for in effect, qualify with CrystalVoice */
5344 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5345 /* if CrystalVoice if off, turn off in effects. */
5346 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5347 val = 0;
5348
5349 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5350 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5351 val = 0;
5352
5353 /* If Voice Focus on SBZ, set to two channel. */
5354 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5355 && (spec->cur_mic_type != REAR_LINE_IN)) {
5356 if (spec->effects_switch[CRYSTAL_VOICE -
5357 EFFECT_START_NID]) {
5358
5359 if (spec->effects_switch[VOICE_FOCUS -
5360 EFFECT_START_NID]) {
5361 tmp = FLOAT_TWO;
5362 val = 1;
5363 } else
5364 tmp = FLOAT_ONE;
5365
5366 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5367 }
5368 }
5369 /*
5370 * For SBZ noise reduction, there's an extra command
5371 * to module ID 0x47. No clue why.
5372 */
5373 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5374 && (spec->cur_mic_type != REAR_LINE_IN)) {
5375 if (spec->effects_switch[CRYSTAL_VOICE -
5376 EFFECT_START_NID]) {
5377 if (spec->effects_switch[NOISE_REDUCTION -
5378 EFFECT_START_NID])
5379 tmp = FLOAT_ONE;
5380 else
5381 tmp = FLOAT_ZERO;
5382 } else
5383 tmp = FLOAT_ZERO;
5384
5385 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5386 }
5387
5388 /* If rear line in disable effects. */
5389 if (ca0132_use_alt_functions(spec) &&
5390 spec->in_enum_val == REAR_LINE_IN)
5391 val = 0;
5392 }
5393
5394 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5395 nid, val);
5396
5397 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5398 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5399 ca0132_effects[idx].reqs[0], on);
5400
5401 if (err < 0)
5402 return 0; /* no changed */
5403
5404 return 1;
5405 }
5406
5407 /*
5408 * Turn on/off Playback Enhancements
5409 */
ca0132_pe_switch_set(struct hda_codec * codec)5410 static int ca0132_pe_switch_set(struct hda_codec *codec)
5411 {
5412 struct ca0132_spec *spec = codec->spec;
5413 hda_nid_t nid;
5414 int i, ret = 0;
5415
5416 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5417 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5418
5419 if (ca0132_use_alt_functions(spec))
5420 ca0132_alt_select_out(codec);
5421
5422 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5423 nid = OUT_EFFECT_START_NID;
5424 /* PE affects all out effects */
5425 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5426 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5427
5428 return ret;
5429 }
5430
5431 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)5432 static int stop_mic1(struct hda_codec *codec)
5433 {
5434 struct ca0132_spec *spec = codec->spec;
5435 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5436 AC_VERB_GET_CONV, 0);
5437 if (oldval != 0)
5438 snd_hda_codec_write(codec, spec->adcs[0], 0,
5439 AC_VERB_SET_CHANNEL_STREAMID,
5440 0);
5441 return oldval;
5442 }
5443
5444 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5445 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5446 {
5447 struct ca0132_spec *spec = codec->spec;
5448 /* Restore the previous stream and channel */
5449 if (oldval != 0)
5450 snd_hda_codec_write(codec, spec->adcs[0], 0,
5451 AC_VERB_SET_CHANNEL_STREAMID,
5452 oldval);
5453 }
5454
5455 /*
5456 * Turn on/off CrystalVoice
5457 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5458 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5459 {
5460 struct ca0132_spec *spec = codec->spec;
5461 hda_nid_t nid;
5462 int i, ret = 0;
5463 unsigned int oldval;
5464
5465 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5466 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5467
5468 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5469 nid = IN_EFFECT_START_NID;
5470 /* CrystalVoice affects all in effects */
5471 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5472 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5473
5474 /* including VoiceFX */
5475 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5476
5477 /* set correct vipsource */
5478 oldval = stop_mic1(codec);
5479 if (ca0132_use_alt_functions(spec))
5480 ret |= ca0132_alt_set_vipsource(codec, 1);
5481 else
5482 ret |= ca0132_set_vipsource(codec, 1);
5483 resume_mic1(codec, oldval);
5484 return ret;
5485 }
5486
ca0132_mic_boost_set(struct hda_codec * codec,long val)5487 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5488 {
5489 struct ca0132_spec *spec = codec->spec;
5490 int ret = 0;
5491
5492 if (val) /* on */
5493 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5494 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5495 else /* off */
5496 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5497 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5498
5499 return ret;
5500 }
5501
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5502 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5503 {
5504 struct ca0132_spec *spec = codec->spec;
5505 int ret = 0;
5506
5507 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5508 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5509 return ret;
5510 }
5511
ae5_headphone_gain_set(struct hda_codec * codec,long val)5512 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5513 {
5514 unsigned int i;
5515
5516 for (i = 0; i < 4; i++)
5517 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5518 ae5_headphone_gain_presets[val].vals[i]);
5519 return 0;
5520 }
5521
5522 /*
5523 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5524 * amplifier to handle a 600 ohm load.
5525 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5526 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5527 {
5528 ca0113_mmio_gpio_set(codec, 1, val);
5529
5530 return 0;
5531 }
5532
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5533 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5534 struct snd_ctl_elem_value *ucontrol)
5535 {
5536 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5537 hda_nid_t nid = get_amp_nid(kcontrol);
5538 hda_nid_t shared_nid = 0;
5539 bool effective;
5540 int ret = 0;
5541 struct ca0132_spec *spec = codec->spec;
5542 int auto_jack;
5543
5544 if (nid == VNID_HP_SEL) {
5545 auto_jack =
5546 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5547 if (!auto_jack) {
5548 if (ca0132_use_alt_functions(spec))
5549 ca0132_alt_select_out(codec);
5550 else
5551 ca0132_select_out(codec);
5552 }
5553 return 1;
5554 }
5555
5556 if (nid == VNID_AMIC1_SEL) {
5557 auto_jack =
5558 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5559 if (!auto_jack)
5560 ca0132_select_mic(codec);
5561 return 1;
5562 }
5563
5564 if (nid == VNID_HP_ASEL) {
5565 if (ca0132_use_alt_functions(spec))
5566 ca0132_alt_select_out(codec);
5567 else
5568 ca0132_select_out(codec);
5569 return 1;
5570 }
5571
5572 if (nid == VNID_AMIC1_ASEL) {
5573 ca0132_select_mic(codec);
5574 return 1;
5575 }
5576
5577 /* if effective conditions, then update hw immediately. */
5578 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5579 if (effective) {
5580 int dir = get_amp_direction(kcontrol);
5581 int ch = get_amp_channels(kcontrol);
5582 unsigned long pval;
5583
5584 mutex_lock(&codec->control_mutex);
5585 pval = kcontrol->private_value;
5586 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5587 0, dir);
5588 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5589 kcontrol->private_value = pval;
5590 mutex_unlock(&codec->control_mutex);
5591 }
5592
5593 return ret;
5594 }
5595 /* End of control change helpers. */
5596
ca0132_alt_bass_redirection_xover_set(struct hda_codec * codec,long idx)5597 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5598 long idx)
5599 {
5600 snd_hda_power_up(codec);
5601
5602 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5603 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5604
5605 snd_hda_power_down(codec);
5606 }
5607
5608 /*
5609 * Below I've added controls to mess with the effect levels, I've only enabled
5610 * them on the Sound Blaster Z, but they would probably also work on the
5611 * Chromebook. I figured they were probably tuned specifically for it, and left
5612 * out for a reason.
5613 */
5614
5615 /* Sets DSP effect level from the sliders above the controls */
5616
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5617 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5618 const unsigned int *lookup, int idx)
5619 {
5620 int i = 0;
5621 unsigned int y;
5622 /*
5623 * For X_BASS, req 2 is actually crossover freq instead of
5624 * effect level
5625 */
5626 if (nid == X_BASS)
5627 y = 2;
5628 else
5629 y = 1;
5630
5631 snd_hda_power_up(codec);
5632 if (nid == XBASS_XOVER) {
5633 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5634 if (ca0132_effects[i].nid == X_BASS)
5635 break;
5636
5637 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5638 ca0132_effects[i].reqs[1],
5639 &(lookup[idx - 1]), sizeof(unsigned int));
5640 } else {
5641 /* Find the actual effect structure */
5642 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5643 if (nid == ca0132_effects[i].nid)
5644 break;
5645
5646 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5647 ca0132_effects[i].reqs[y],
5648 &(lookup[idx]), sizeof(unsigned int));
5649 }
5650
5651 snd_hda_power_down(codec);
5652
5653 return 0;
5654 }
5655
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5656 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5657 struct snd_ctl_elem_value *ucontrol)
5658 {
5659 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5660 struct ca0132_spec *spec = codec->spec;
5661 long *valp = ucontrol->value.integer.value;
5662 hda_nid_t nid = get_amp_nid(kcontrol);
5663
5664 if (nid == BASS_REDIRECTION_XOVER)
5665 *valp = spec->bass_redirect_xover_freq;
5666 else
5667 *valp = spec->xbass_xover_freq;
5668
5669 return 0;
5670 }
5671
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5672 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5673 struct snd_ctl_elem_value *ucontrol)
5674 {
5675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5676 struct ca0132_spec *spec = codec->spec;
5677 hda_nid_t nid = get_amp_nid(kcontrol);
5678 long *valp = ucontrol->value.integer.value;
5679 int idx = nid - OUT_EFFECT_START_NID;
5680
5681 *valp = spec->fx_ctl_val[idx];
5682 return 0;
5683 }
5684
5685 /*
5686 * The X-bass crossover starts at 10hz, so the min is 1. The
5687 * frequency is set in multiples of 10.
5688 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5689 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5690 struct snd_ctl_elem_info *uinfo)
5691 {
5692 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5693 uinfo->count = 1;
5694 uinfo->value.integer.min = 1;
5695 uinfo->value.integer.max = 100;
5696 uinfo->value.integer.step = 1;
5697
5698 return 0;
5699 }
5700
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5701 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5702 struct snd_ctl_elem_info *uinfo)
5703 {
5704 int chs = get_amp_channels(kcontrol);
5705
5706 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5707 uinfo->count = chs == 3 ? 2 : 1;
5708 uinfo->value.integer.min = 0;
5709 uinfo->value.integer.max = 100;
5710 uinfo->value.integer.step = 1;
5711
5712 return 0;
5713 }
5714
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5715 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5716 struct snd_ctl_elem_value *ucontrol)
5717 {
5718 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5719 struct ca0132_spec *spec = codec->spec;
5720 hda_nid_t nid = get_amp_nid(kcontrol);
5721 long *valp = ucontrol->value.integer.value;
5722 long *cur_val;
5723 int idx;
5724
5725 if (nid == BASS_REDIRECTION_XOVER)
5726 cur_val = &spec->bass_redirect_xover_freq;
5727 else
5728 cur_val = &spec->xbass_xover_freq;
5729
5730 /* any change? */
5731 if (*cur_val == *valp)
5732 return 0;
5733
5734 *cur_val = *valp;
5735
5736 idx = *valp;
5737 if (nid == BASS_REDIRECTION_XOVER)
5738 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5739 else
5740 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5741
5742 return 0;
5743 }
5744
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5745 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5746 struct snd_ctl_elem_value *ucontrol)
5747 {
5748 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5749 struct ca0132_spec *spec = codec->spec;
5750 hda_nid_t nid = get_amp_nid(kcontrol);
5751 long *valp = ucontrol->value.integer.value;
5752 int idx;
5753
5754 idx = nid - EFFECT_START_NID;
5755 /* any change? */
5756 if (spec->fx_ctl_val[idx] == *valp)
5757 return 0;
5758
5759 spec->fx_ctl_val[idx] = *valp;
5760
5761 idx = *valp;
5762 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5763
5764 return 0;
5765 }
5766
5767
5768 /*
5769 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5770 * only has off or full 30 dB, and didn't like making a volume slider that has
5771 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5772 */
5773 #define MIC_BOOST_NUM_OF_STEPS 4
5774 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5775
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5776 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5777 struct snd_ctl_elem_info *uinfo)
5778 {
5779 char *sfx = "dB";
5780 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5781
5782 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5783 uinfo->count = 1;
5784 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5785 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5786 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5787 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5788 strcpy(uinfo->value.enumerated.name, namestr);
5789 return 0;
5790 }
5791
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5792 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5793 struct snd_ctl_elem_value *ucontrol)
5794 {
5795 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5796 struct ca0132_spec *spec = codec->spec;
5797
5798 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5799 return 0;
5800 }
5801
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5802 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5803 struct snd_ctl_elem_value *ucontrol)
5804 {
5805 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5806 struct ca0132_spec *spec = codec->spec;
5807 int sel = ucontrol->value.enumerated.item[0];
5808 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5809
5810 if (sel >= items)
5811 return 0;
5812
5813 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5814 sel);
5815
5816 spec->mic_boost_enum_val = sel;
5817
5818 if (spec->in_enum_val != REAR_LINE_IN)
5819 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5820
5821 return 1;
5822 }
5823
5824 /*
5825 * Sound BlasterX AE-5 Headphone Gain Controls.
5826 */
5827 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5828 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5829 struct snd_ctl_elem_info *uinfo)
5830 {
5831 char *sfx = " Ohms)";
5832 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5833
5834 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5835 uinfo->count = 1;
5836 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5837 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5838 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5839 sprintf(namestr, "%s %s",
5840 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5841 sfx);
5842 strcpy(uinfo->value.enumerated.name, namestr);
5843 return 0;
5844 }
5845
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5846 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5847 struct snd_ctl_elem_value *ucontrol)
5848 {
5849 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5850 struct ca0132_spec *spec = codec->spec;
5851
5852 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5853 return 0;
5854 }
5855
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5856 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5857 struct snd_ctl_elem_value *ucontrol)
5858 {
5859 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5860 struct ca0132_spec *spec = codec->spec;
5861 int sel = ucontrol->value.enumerated.item[0];
5862 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5863
5864 if (sel >= items)
5865 return 0;
5866
5867 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5868 sel);
5869
5870 spec->ae5_headphone_gain_val = sel;
5871
5872 if (spec->out_enum_val == HEADPHONE_OUT)
5873 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5874
5875 return 1;
5876 }
5877
5878 /*
5879 * Sound BlasterX AE-5 sound filter enumerated control.
5880 */
5881 #define AE5_SOUND_FILTER_MAX 3
5882
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5883 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5884 struct snd_ctl_elem_info *uinfo)
5885 {
5886 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5887
5888 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5889 uinfo->count = 1;
5890 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5891 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5892 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5893 sprintf(namestr, "%s",
5894 ae5_filter_presets[uinfo->value.enumerated.item].name);
5895 strcpy(uinfo->value.enumerated.name, namestr);
5896 return 0;
5897 }
5898
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5899 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5900 struct snd_ctl_elem_value *ucontrol)
5901 {
5902 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5903 struct ca0132_spec *spec = codec->spec;
5904
5905 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5906 return 0;
5907 }
5908
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5909 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5910 struct snd_ctl_elem_value *ucontrol)
5911 {
5912 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5913 struct ca0132_spec *spec = codec->spec;
5914 int sel = ucontrol->value.enumerated.item[0];
5915 unsigned int items = AE5_SOUND_FILTER_MAX;
5916
5917 if (sel >= items)
5918 return 0;
5919
5920 codec_dbg(codec, "ae5_sound_filter: %s\n",
5921 ae5_filter_presets[sel].name);
5922
5923 spec->ae5_filter_val = sel;
5924
5925 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5926 ae5_filter_presets[sel].val);
5927
5928 return 1;
5929 }
5930
5931 /*
5932 * Input Select Control for alternative ca0132 codecs. This exists because
5933 * front microphone has no auto-detect, and we need a way to set the rear
5934 * as line-in
5935 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5936 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5937 struct snd_ctl_elem_info *uinfo)
5938 {
5939 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5940 uinfo->count = 1;
5941 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5942 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5943 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5944 strcpy(uinfo->value.enumerated.name,
5945 in_src_str[uinfo->value.enumerated.item]);
5946 return 0;
5947 }
5948
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5949 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5950 struct snd_ctl_elem_value *ucontrol)
5951 {
5952 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5953 struct ca0132_spec *spec = codec->spec;
5954
5955 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5956 return 0;
5957 }
5958
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5959 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5960 struct snd_ctl_elem_value *ucontrol)
5961 {
5962 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5963 struct ca0132_spec *spec = codec->spec;
5964 int sel = ucontrol->value.enumerated.item[0];
5965 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5966
5967 /*
5968 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5969 * line-in.
5970 */
5971 if (ca0132_quirk(spec) == QUIRK_AE7)
5972 items = 2;
5973
5974 if (sel >= items)
5975 return 0;
5976
5977 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5978 sel, in_src_str[sel]);
5979
5980 spec->in_enum_val = sel;
5981
5982 ca0132_alt_select_in(codec);
5983
5984 return 1;
5985 }
5986
5987 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5988 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5989 struct snd_ctl_elem_info *uinfo)
5990 {
5991 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5992 uinfo->count = 1;
5993 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5994 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5995 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5996 strcpy(uinfo->value.enumerated.name,
5997 out_type_str[uinfo->value.enumerated.item]);
5998 return 0;
5999 }
6000
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6001 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
6002 struct snd_ctl_elem_value *ucontrol)
6003 {
6004 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6005 struct ca0132_spec *spec = codec->spec;
6006
6007 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6008 return 0;
6009 }
6010
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6011 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6012 struct snd_ctl_elem_value *ucontrol)
6013 {
6014 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6015 struct ca0132_spec *spec = codec->spec;
6016 int sel = ucontrol->value.enumerated.item[0];
6017 unsigned int items = NUM_OF_OUTPUTS;
6018 unsigned int auto_jack;
6019
6020 if (sel >= items)
6021 return 0;
6022
6023 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6024 sel, out_type_str[sel]);
6025
6026 spec->out_enum_val = sel;
6027
6028 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6029
6030 if (!auto_jack)
6031 ca0132_alt_select_out(codec);
6032
6033 return 1;
6034 }
6035
6036 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6037 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6038 struct snd_ctl_elem_info *uinfo)
6039 {
6040 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6041
6042 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6043 uinfo->count = 1;
6044 uinfo->value.enumerated.items = items;
6045 if (uinfo->value.enumerated.item >= items)
6046 uinfo->value.enumerated.item = items - 1;
6047 strcpy(uinfo->value.enumerated.name,
6048 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6049 return 0;
6050 }
6051
ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6052 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6053 struct snd_ctl_elem_value *ucontrol)
6054 {
6055 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6056 struct ca0132_spec *spec = codec->spec;
6057
6058 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6059 return 0;
6060 }
6061
ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6062 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6063 struct snd_ctl_elem_value *ucontrol)
6064 {
6065 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6066 struct ca0132_spec *spec = codec->spec;
6067 int sel = ucontrol->value.enumerated.item[0];
6068 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6069
6070 if (sel >= items)
6071 return 0;
6072
6073 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6074 sel, speaker_channel_cfgs[sel].name);
6075
6076 spec->channel_cfg_val = sel;
6077
6078 if (spec->out_enum_val == SPEAKER_OUT)
6079 ca0132_alt_select_out(codec);
6080
6081 return 1;
6082 }
6083
6084 /*
6085 * Smart Volume output setting control. Three different settings, Normal,
6086 * which takes the value from the smart volume slider. The two others, loud
6087 * and night, disregard the slider value and have uneditable values.
6088 */
6089 #define NUM_OF_SVM_SETTINGS 3
6090 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6091
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6092 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6093 struct snd_ctl_elem_info *uinfo)
6094 {
6095 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6096 uinfo->count = 1;
6097 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6098 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6099 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6100 strcpy(uinfo->value.enumerated.name,
6101 out_svm_set_enum_str[uinfo->value.enumerated.item]);
6102 return 0;
6103 }
6104
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6105 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6106 struct snd_ctl_elem_value *ucontrol)
6107 {
6108 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6109 struct ca0132_spec *spec = codec->spec;
6110
6111 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6112 return 0;
6113 }
6114
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6115 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6116 struct snd_ctl_elem_value *ucontrol)
6117 {
6118 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6119 struct ca0132_spec *spec = codec->spec;
6120 int sel = ucontrol->value.enumerated.item[0];
6121 unsigned int items = NUM_OF_SVM_SETTINGS;
6122 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6123 unsigned int tmp;
6124
6125 if (sel >= items)
6126 return 0;
6127
6128 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6129 sel, out_svm_set_enum_str[sel]);
6130
6131 spec->smart_volume_setting = sel;
6132
6133 switch (sel) {
6134 case 0:
6135 tmp = FLOAT_ZERO;
6136 break;
6137 case 1:
6138 tmp = FLOAT_ONE;
6139 break;
6140 case 2:
6141 tmp = FLOAT_TWO;
6142 break;
6143 default:
6144 tmp = FLOAT_ZERO;
6145 break;
6146 }
6147 /* Req 2 is the Smart Volume Setting req. */
6148 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6149 ca0132_effects[idx].reqs[2], tmp);
6150 return 1;
6151 }
6152
6153 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6154 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6155 struct snd_ctl_elem_info *uinfo)
6156 {
6157 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6158
6159 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6160 uinfo->count = 1;
6161 uinfo->value.enumerated.items = items;
6162 if (uinfo->value.enumerated.item >= items)
6163 uinfo->value.enumerated.item = items - 1;
6164 strcpy(uinfo->value.enumerated.name,
6165 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6166 return 0;
6167 }
6168
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6169 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6170 struct snd_ctl_elem_value *ucontrol)
6171 {
6172 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6173 struct ca0132_spec *spec = codec->spec;
6174
6175 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6176 return 0;
6177 }
6178
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6179 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6180 struct snd_ctl_elem_value *ucontrol)
6181 {
6182 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6183 struct ca0132_spec *spec = codec->spec;
6184 int i, err = 0;
6185 int sel = ucontrol->value.enumerated.item[0];
6186 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6187
6188 if (sel >= items)
6189 return 0;
6190
6191 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6192 ca0132_alt_eq_presets[sel].name);
6193 /*
6194 * Idx 0 is default.
6195 * Default needs to qualify with CrystalVoice state.
6196 */
6197 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6198 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6199 ca0132_alt_eq_enum.reqs[i],
6200 ca0132_alt_eq_presets[sel].vals[i]);
6201 if (err < 0)
6202 break;
6203 }
6204
6205 if (err >= 0)
6206 spec->eq_preset_val = sel;
6207
6208 return 1;
6209 }
6210
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6211 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6212 struct snd_ctl_elem_info *uinfo)
6213 {
6214 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6215
6216 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6217 uinfo->count = 1;
6218 uinfo->value.enumerated.items = items;
6219 if (uinfo->value.enumerated.item >= items)
6220 uinfo->value.enumerated.item = items - 1;
6221 strcpy(uinfo->value.enumerated.name,
6222 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6223 return 0;
6224 }
6225
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6226 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6227 struct snd_ctl_elem_value *ucontrol)
6228 {
6229 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6230 struct ca0132_spec *spec = codec->spec;
6231
6232 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6233 return 0;
6234 }
6235
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6236 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6237 struct snd_ctl_elem_value *ucontrol)
6238 {
6239 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6240 struct ca0132_spec *spec = codec->spec;
6241 int i, err = 0;
6242 int sel = ucontrol->value.enumerated.item[0];
6243
6244 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6245 return 0;
6246
6247 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6248 sel, ca0132_voicefx_presets[sel].name);
6249
6250 /*
6251 * Idx 0 is default.
6252 * Default needs to qualify with CrystalVoice state.
6253 */
6254 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6255 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6256 ca0132_voicefx.reqs[i],
6257 ca0132_voicefx_presets[sel].vals[i]);
6258 if (err < 0)
6259 break;
6260 }
6261
6262 if (err >= 0) {
6263 spec->voicefx_val = sel;
6264 /* enable voice fx */
6265 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6266 }
6267
6268 return 1;
6269 }
6270
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6271 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6272 struct snd_ctl_elem_value *ucontrol)
6273 {
6274 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6275 struct ca0132_spec *spec = codec->spec;
6276 hda_nid_t nid = get_amp_nid(kcontrol);
6277 int ch = get_amp_channels(kcontrol);
6278 long *valp = ucontrol->value.integer.value;
6279
6280 /* vnode */
6281 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6282 if (ch & 1) {
6283 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6284 valp++;
6285 }
6286 if (ch & 2) {
6287 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6288 valp++;
6289 }
6290 return 0;
6291 }
6292
6293 /* effects, include PE and CrystalVoice */
6294 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6295 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6296 return 0;
6297 }
6298
6299 /* mic boost */
6300 if (nid == spec->input_pins[0]) {
6301 *valp = spec->cur_mic_boost;
6302 return 0;
6303 }
6304
6305 if (nid == ZXR_HEADPHONE_GAIN) {
6306 *valp = spec->zxr_gain_set;
6307 return 0;
6308 }
6309
6310 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6311 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6312 return 0;
6313 }
6314
6315 if (nid == BASS_REDIRECTION) {
6316 *valp = spec->bass_redirection_val;
6317 return 0;
6318 }
6319
6320 return 0;
6321 }
6322
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6323 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6324 struct snd_ctl_elem_value *ucontrol)
6325 {
6326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6327 struct ca0132_spec *spec = codec->spec;
6328 hda_nid_t nid = get_amp_nid(kcontrol);
6329 int ch = get_amp_channels(kcontrol);
6330 long *valp = ucontrol->value.integer.value;
6331 int changed = 1;
6332
6333 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6334 nid, *valp);
6335
6336 snd_hda_power_up(codec);
6337 /* vnode */
6338 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6339 if (ch & 1) {
6340 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6341 valp++;
6342 }
6343 if (ch & 2) {
6344 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6345 valp++;
6346 }
6347 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6348 goto exit;
6349 }
6350
6351 /* PE */
6352 if (nid == PLAY_ENHANCEMENT) {
6353 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6354 changed = ca0132_pe_switch_set(codec);
6355 goto exit;
6356 }
6357
6358 /* CrystalVoice */
6359 if (nid == CRYSTAL_VOICE) {
6360 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6361 changed = ca0132_cvoice_switch_set(codec);
6362 goto exit;
6363 }
6364
6365 /* out and in effects */
6366 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6367 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6368 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6369 changed = ca0132_effects_set(codec, nid, *valp);
6370 goto exit;
6371 }
6372
6373 /* mic boost */
6374 if (nid == spec->input_pins[0]) {
6375 spec->cur_mic_boost = *valp;
6376 if (ca0132_use_alt_functions(spec)) {
6377 if (spec->in_enum_val != REAR_LINE_IN)
6378 changed = ca0132_mic_boost_set(codec, *valp);
6379 } else {
6380 /* Mic boost does not apply to Digital Mic */
6381 if (spec->cur_mic_type != DIGITAL_MIC)
6382 changed = ca0132_mic_boost_set(codec, *valp);
6383 }
6384
6385 goto exit;
6386 }
6387
6388 if (nid == ZXR_HEADPHONE_GAIN) {
6389 spec->zxr_gain_set = *valp;
6390 if (spec->cur_out_type == HEADPHONE_OUT)
6391 changed = zxr_headphone_gain_set(codec, *valp);
6392 else
6393 changed = 0;
6394
6395 goto exit;
6396 }
6397
6398 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6399 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6400 if (spec->cur_out_type == SPEAKER_OUT)
6401 ca0132_alt_set_full_range_speaker(codec);
6402
6403 changed = 0;
6404 }
6405
6406 if (nid == BASS_REDIRECTION) {
6407 spec->bass_redirection_val = *valp;
6408 if (spec->cur_out_type == SPEAKER_OUT)
6409 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6410
6411 changed = 0;
6412 }
6413
6414 exit:
6415 snd_hda_power_down(codec);
6416 return changed;
6417 }
6418
6419 /*
6420 * Volume related
6421 */
6422 /*
6423 * Sets the internal DSP decibel level to match the DAC for output, and the
6424 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6425 * all alternative codecs set DSP playback volume.
6426 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)6427 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6428 {
6429 struct ca0132_spec *spec = codec->spec;
6430 unsigned int dsp_dir;
6431 unsigned int lookup_val;
6432
6433 if (nid == VNID_SPK)
6434 dsp_dir = DSP_VOL_OUT;
6435 else
6436 dsp_dir = DSP_VOL_IN;
6437
6438 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6439
6440 dspio_set_uint_param(codec,
6441 ca0132_alt_vol_ctls[dsp_dir].mid,
6442 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6443 float_vol_db_lookup[lookup_val]);
6444
6445 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6446
6447 dspio_set_uint_param(codec,
6448 ca0132_alt_vol_ctls[dsp_dir].mid,
6449 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6450 float_vol_db_lookup[lookup_val]);
6451
6452 dspio_set_uint_param(codec,
6453 ca0132_alt_vol_ctls[dsp_dir].mid,
6454 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6455 }
6456
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6457 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6458 struct snd_ctl_elem_info *uinfo)
6459 {
6460 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6461 struct ca0132_spec *spec = codec->spec;
6462 hda_nid_t nid = get_amp_nid(kcontrol);
6463 int ch = get_amp_channels(kcontrol);
6464 int dir = get_amp_direction(kcontrol);
6465 unsigned long pval;
6466 int err;
6467
6468 switch (nid) {
6469 case VNID_SPK:
6470 /* follow shared_out info */
6471 nid = spec->shared_out_nid;
6472 mutex_lock(&codec->control_mutex);
6473 pval = kcontrol->private_value;
6474 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6475 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6476 kcontrol->private_value = pval;
6477 mutex_unlock(&codec->control_mutex);
6478 break;
6479 case VNID_MIC:
6480 /* follow shared_mic info */
6481 nid = spec->shared_mic_nid;
6482 mutex_lock(&codec->control_mutex);
6483 pval = kcontrol->private_value;
6484 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6485 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6486 kcontrol->private_value = pval;
6487 mutex_unlock(&codec->control_mutex);
6488 break;
6489 default:
6490 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6491 }
6492 return err;
6493 }
6494
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6495 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6496 struct snd_ctl_elem_value *ucontrol)
6497 {
6498 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6499 struct ca0132_spec *spec = codec->spec;
6500 hda_nid_t nid = get_amp_nid(kcontrol);
6501 int ch = get_amp_channels(kcontrol);
6502 long *valp = ucontrol->value.integer.value;
6503
6504 /* store the left and right volume */
6505 if (ch & 1) {
6506 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6507 valp++;
6508 }
6509 if (ch & 2) {
6510 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6511 valp++;
6512 }
6513 return 0;
6514 }
6515
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6516 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6517 struct snd_ctl_elem_value *ucontrol)
6518 {
6519 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6520 struct ca0132_spec *spec = codec->spec;
6521 hda_nid_t nid = get_amp_nid(kcontrol);
6522 int ch = get_amp_channels(kcontrol);
6523 long *valp = ucontrol->value.integer.value;
6524 hda_nid_t shared_nid = 0;
6525 bool effective;
6526 int changed = 1;
6527
6528 /* store the left and right volume */
6529 if (ch & 1) {
6530 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6531 valp++;
6532 }
6533 if (ch & 2) {
6534 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6535 valp++;
6536 }
6537
6538 /* if effective conditions, then update hw immediately. */
6539 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6540 if (effective) {
6541 int dir = get_amp_direction(kcontrol);
6542 unsigned long pval;
6543
6544 snd_hda_power_up(codec);
6545 mutex_lock(&codec->control_mutex);
6546 pval = kcontrol->private_value;
6547 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6548 0, dir);
6549 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6550 kcontrol->private_value = pval;
6551 mutex_unlock(&codec->control_mutex);
6552 snd_hda_power_down(codec);
6553 }
6554
6555 return changed;
6556 }
6557
6558 /*
6559 * This function is the same as the one above, because using an if statement
6560 * inside of the above volume control for the DSP volume would cause too much
6561 * lag. This is a lot more smooth.
6562 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6563 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6564 struct snd_ctl_elem_value *ucontrol)
6565 {
6566 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6567 struct ca0132_spec *spec = codec->spec;
6568 hda_nid_t nid = get_amp_nid(kcontrol);
6569 int ch = get_amp_channels(kcontrol);
6570 long *valp = ucontrol->value.integer.value;
6571 hda_nid_t vnid = 0;
6572 int changed;
6573
6574 switch (nid) {
6575 case 0x02:
6576 vnid = VNID_SPK;
6577 break;
6578 case 0x07:
6579 vnid = VNID_MIC;
6580 break;
6581 }
6582
6583 /* store the left and right volume */
6584 if (ch & 1) {
6585 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6586 valp++;
6587 }
6588 if (ch & 2) {
6589 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6590 valp++;
6591 }
6592
6593 snd_hda_power_up(codec);
6594 ca0132_alt_dsp_volume_put(codec, vnid);
6595 mutex_lock(&codec->control_mutex);
6596 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6597 mutex_unlock(&codec->control_mutex);
6598 snd_hda_power_down(codec);
6599
6600 return changed;
6601 }
6602
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6603 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6604 unsigned int size, unsigned int __user *tlv)
6605 {
6606 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6607 struct ca0132_spec *spec = codec->spec;
6608 hda_nid_t nid = get_amp_nid(kcontrol);
6609 int ch = get_amp_channels(kcontrol);
6610 int dir = get_amp_direction(kcontrol);
6611 unsigned long pval;
6612 int err;
6613
6614 switch (nid) {
6615 case VNID_SPK:
6616 /* follow shared_out tlv */
6617 nid = spec->shared_out_nid;
6618 mutex_lock(&codec->control_mutex);
6619 pval = kcontrol->private_value;
6620 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6621 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6622 kcontrol->private_value = pval;
6623 mutex_unlock(&codec->control_mutex);
6624 break;
6625 case VNID_MIC:
6626 /* follow shared_mic tlv */
6627 nid = spec->shared_mic_nid;
6628 mutex_lock(&codec->control_mutex);
6629 pval = kcontrol->private_value;
6630 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6631 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6632 kcontrol->private_value = pval;
6633 mutex_unlock(&codec->control_mutex);
6634 break;
6635 default:
6636 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6637 }
6638 return err;
6639 }
6640
6641 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6642 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6643 const char *pfx, int dir)
6644 {
6645 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6646 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6647 struct snd_kcontrol_new knew =
6648 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6649
6650 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6651
6652 knew.tlv.c = NULL;
6653
6654 switch (nid) {
6655 case XBASS_XOVER:
6656 knew.info = ca0132_alt_xbass_xover_slider_info;
6657 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6658 knew.put = ca0132_alt_xbass_xover_slider_put;
6659 break;
6660 default:
6661 knew.info = ca0132_alt_effect_slider_info;
6662 knew.get = ca0132_alt_slider_ctl_get;
6663 knew.put = ca0132_alt_effect_slider_put;
6664 knew.private_value =
6665 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6666 break;
6667 }
6668
6669 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6670 }
6671
6672 /*
6673 * Added FX: prefix for the alternative codecs, because otherwise the surround
6674 * effect would conflict with the Surround sound volume control. Also seems more
6675 * clear as to what the switches do. Left alone for others.
6676 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6677 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6678 const char *pfx, int dir)
6679 {
6680 struct ca0132_spec *spec = codec->spec;
6681 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6682 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6683 struct snd_kcontrol_new knew =
6684 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6685 /* If using alt_controls, add FX: prefix. But, don't add FX:
6686 * prefix to OutFX or InFX enable controls.
6687 */
6688 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6689 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6690 else
6691 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6692
6693 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6694 }
6695
add_voicefx(struct hda_codec * codec)6696 static int add_voicefx(struct hda_codec *codec)
6697 {
6698 struct snd_kcontrol_new knew =
6699 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6700 VOICEFX, 1, 0, HDA_INPUT);
6701 knew.info = ca0132_voicefx_info;
6702 knew.get = ca0132_voicefx_get;
6703 knew.put = ca0132_voicefx_put;
6704 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6705 }
6706
6707 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6708 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6709 {
6710 struct snd_kcontrol_new knew =
6711 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6712 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6713 knew.info = ca0132_alt_eq_preset_info;
6714 knew.get = ca0132_alt_eq_preset_get;
6715 knew.put = ca0132_alt_eq_preset_put;
6716 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6717 snd_ctl_new1(&knew, codec));
6718 }
6719
6720 /*
6721 * Add enumerated control for the three different settings of the smart volume
6722 * output effect. Normal just uses the slider value, and loud and night are
6723 * their own things that ignore that value.
6724 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6725 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6726 {
6727 struct snd_kcontrol_new knew =
6728 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6729 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6730 knew.info = ca0132_alt_svm_setting_info;
6731 knew.get = ca0132_alt_svm_setting_get;
6732 knew.put = ca0132_alt_svm_setting_put;
6733 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6734 snd_ctl_new1(&knew, codec));
6735
6736 }
6737
6738 /*
6739 * Create an Output Select enumerated control for codecs with surround
6740 * out capabilities.
6741 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6742 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6743 {
6744 struct snd_kcontrol_new knew =
6745 HDA_CODEC_MUTE_MONO("Output Select",
6746 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6747 knew.info = ca0132_alt_output_select_get_info;
6748 knew.get = ca0132_alt_output_select_get;
6749 knew.put = ca0132_alt_output_select_put;
6750 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6751 snd_ctl_new1(&knew, codec));
6752 }
6753
6754 /*
6755 * Add a control for selecting channel count on speaker output. Setting this
6756 * allows the DSP to do bass redirection and channel upmixing on surround
6757 * configurations.
6758 */
ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec * codec)6759 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6760 {
6761 struct snd_kcontrol_new knew =
6762 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6763 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6764 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6765 knew.get = ca0132_alt_speaker_channel_cfg_get;
6766 knew.put = ca0132_alt_speaker_channel_cfg_put;
6767 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6768 snd_ctl_new1(&knew, codec));
6769 }
6770
6771 /*
6772 * Full range front stereo and rear surround switches. When these are set to
6773 * full range, the lower frequencies from these channels are no longer
6774 * redirected to the LFE channel.
6775 */
ca0132_alt_add_front_full_range_switch(struct hda_codec * codec)6776 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6777 {
6778 struct snd_kcontrol_new knew =
6779 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6780 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6781
6782 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6783 snd_ctl_new1(&knew, codec));
6784 }
6785
ca0132_alt_add_rear_full_range_switch(struct hda_codec * codec)6786 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6787 {
6788 struct snd_kcontrol_new knew =
6789 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6790 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6791
6792 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6793 snd_ctl_new1(&knew, codec));
6794 }
6795
6796 /*
6797 * Bass redirection redirects audio below the crossover frequency to the LFE
6798 * channel on speakers that are set as not being full-range. On configurations
6799 * without an LFE channel, it does nothing. Bass redirection seems to be the
6800 * replacement for X-Bass on configurations with an LFE channel.
6801 */
ca0132_alt_add_bass_redirection_crossover(struct hda_codec * codec)6802 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6803 {
6804 const char *namestr = "Bass Redirection Crossover";
6805 struct snd_kcontrol_new knew =
6806 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6807 HDA_OUTPUT);
6808
6809 knew.tlv.c = NULL;
6810 knew.info = ca0132_alt_xbass_xover_slider_info;
6811 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6812 knew.put = ca0132_alt_xbass_xover_slider_put;
6813
6814 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6815 snd_ctl_new1(&knew, codec));
6816 }
6817
ca0132_alt_add_bass_redirection_switch(struct hda_codec * codec)6818 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6819 {
6820 const char *namestr = "Bass Redirection";
6821 struct snd_kcontrol_new knew =
6822 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6823 HDA_OUTPUT);
6824
6825 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6826 snd_ctl_new1(&knew, codec));
6827 }
6828
6829 /*
6830 * Create an Input Source enumerated control for the alternate ca0132 codecs
6831 * because the front microphone has no auto-detect, and Line-in has to be set
6832 * somehow.
6833 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6834 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6835 {
6836 struct snd_kcontrol_new knew =
6837 HDA_CODEC_MUTE_MONO("Input Source",
6838 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6839 knew.info = ca0132_alt_input_source_info;
6840 knew.get = ca0132_alt_input_source_get;
6841 knew.put = ca0132_alt_input_source_put;
6842 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6843 snd_ctl_new1(&knew, codec));
6844 }
6845
6846 /*
6847 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6848 * more control than the original mic boost, which is either full 30dB or off.
6849 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6850 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6851 {
6852 struct snd_kcontrol_new knew =
6853 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6854 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6855 knew.info = ca0132_alt_mic_boost_info;
6856 knew.get = ca0132_alt_mic_boost_get;
6857 knew.put = ca0132_alt_mic_boost_put;
6858 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6859 snd_ctl_new1(&knew, codec));
6860
6861 }
6862
6863 /*
6864 * Add headphone gain enumerated control for the AE-5. This switches between
6865 * three modes, low, medium, and high. When non-headphone outputs are selected,
6866 * it is automatically set to high. This is the same behavior as Windows.
6867 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6868 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6869 {
6870 struct snd_kcontrol_new knew =
6871 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6872 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6873 knew.info = ae5_headphone_gain_info;
6874 knew.get = ae5_headphone_gain_get;
6875 knew.put = ae5_headphone_gain_put;
6876 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6877 snd_ctl_new1(&knew, codec));
6878 }
6879
6880 /*
6881 * Add sound filter enumerated control for the AE-5. This adds three different
6882 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6883 * read into it, it changes the DAC's interpolation filter.
6884 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6885 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6886 {
6887 struct snd_kcontrol_new knew =
6888 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6889 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6890 knew.info = ae5_sound_filter_info;
6891 knew.get = ae5_sound_filter_get;
6892 knew.put = ae5_sound_filter_put;
6893 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6894 snd_ctl_new1(&knew, codec));
6895 }
6896
zxr_add_headphone_gain_switch(struct hda_codec * codec)6897 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6898 {
6899 struct snd_kcontrol_new knew =
6900 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6901 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6902
6903 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6904 snd_ctl_new1(&knew, codec));
6905 }
6906
6907 /*
6908 * Need to create follower controls for the alternate codecs that have surround
6909 * capabilities.
6910 */
6911 static const char * const ca0132_alt_follower_pfxs[] = {
6912 "Front", "Surround", "Center", "LFE", NULL,
6913 };
6914
6915 /*
6916 * Also need special channel map, because the default one is incorrect.
6917 * I think this has to do with the pin for rear surround being 0x11,
6918 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6919 */
6920 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6921 { .channels = 2,
6922 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6923 { .channels = 4,
6924 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6925 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6926 { .channels = 6,
6927 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6928 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6929 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6930 { }
6931 };
6932
6933 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6934 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6935 {
6936 int err = 0;
6937 struct hda_pcm *pcm;
6938
6939 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6940 struct hda_pcm_stream *hinfo =
6941 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6942 struct snd_pcm_chmap *chmap;
6943 const struct snd_pcm_chmap_elem *elem;
6944
6945 elem = ca0132_alt_chmaps;
6946 if (hinfo->channels_max == 6) {
6947 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6948 SNDRV_PCM_STREAM_PLAYBACK,
6949 elem, hinfo->channels_max, 0, &chmap);
6950 if (err < 0)
6951 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6952 }
6953 }
6954 }
6955
6956 /*
6957 * When changing Node IDs for Mixer Controls below, make sure to update
6958 * Node IDs in ca0132_config() as well.
6959 */
6960 static const struct snd_kcontrol_new ca0132_mixer[] = {
6961 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6962 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6963 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6964 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6965 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6966 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6967 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6968 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6969 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6970 0x12, 1, HDA_INPUT),
6971 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6972 VNID_HP_SEL, 1, HDA_OUTPUT),
6973 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6974 VNID_AMIC1_SEL, 1, HDA_INPUT),
6975 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6976 VNID_HP_ASEL, 1, HDA_OUTPUT),
6977 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6978 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6979 { } /* end */
6980 };
6981
6982 /*
6983 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6984 * surround controls. Also sets both the Front Playback and Capture Volume
6985 * controls to alt so they set the DSP's decibel level.
6986 */
6987 static const struct snd_kcontrol_new desktop_mixer[] = {
6988 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6989 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6990 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6991 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6992 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6993 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6994 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6995 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6996 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6997 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6998 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6999 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7000 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7001 VNID_HP_ASEL, 1, HDA_OUTPUT),
7002 { } /* end */
7003 };
7004
7005 /*
7006 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7007 * because it doesn't set decibel levels for the DSP for capture.
7008 */
7009 static const struct snd_kcontrol_new r3di_mixer[] = {
7010 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7011 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7012 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7013 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7014 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7015 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7016 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7017 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7018 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7019 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7020 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7021 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7022 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7023 VNID_HP_ASEL, 1, HDA_OUTPUT),
7024 { } /* end */
7025 };
7026
ca0132_build_controls(struct hda_codec * codec)7027 static int ca0132_build_controls(struct hda_codec *codec)
7028 {
7029 struct ca0132_spec *spec = codec->spec;
7030 int i, num_fx, num_sliders;
7031 int err = 0;
7032
7033 /* Add Mixer controls */
7034 for (i = 0; i < spec->num_mixers; i++) {
7035 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7036 if (err < 0)
7037 return err;
7038 }
7039 /* Setup vmaster with surround followers for desktop ca0132 devices */
7040 if (ca0132_use_alt_functions(spec)) {
7041 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7042 spec->tlv);
7043 snd_hda_add_vmaster(codec, "Master Playback Volume",
7044 spec->tlv, ca0132_alt_follower_pfxs,
7045 "Playback Volume", 0);
7046 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7047 NULL, ca0132_alt_follower_pfxs,
7048 "Playback Switch",
7049 true, 0, &spec->vmaster_mute.sw_kctl);
7050 if (err < 0)
7051 return err;
7052 }
7053
7054 /* Add in and out effects controls.
7055 * VoiceFX, PE and CrystalVoice are added separately.
7056 */
7057 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7058 for (i = 0; i < num_fx; i++) {
7059 /* Desktop cards break if Echo Cancellation is used. */
7060 if (ca0132_use_pci_mmio(spec)) {
7061 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7062 OUT_EFFECTS_COUNT))
7063 continue;
7064 }
7065
7066 err = add_fx_switch(codec, ca0132_effects[i].nid,
7067 ca0132_effects[i].name,
7068 ca0132_effects[i].direct);
7069 if (err < 0)
7070 return err;
7071 }
7072 /*
7073 * If codec has use_alt_controls set to true, add effect level sliders,
7074 * EQ presets, and Smart Volume presets. Also, change names to add FX
7075 * prefix, and change PlayEnhancement and CrystalVoice to match.
7076 */
7077 if (ca0132_use_alt_controls(spec)) {
7078 err = ca0132_alt_add_svm_enum(codec);
7079 if (err < 0)
7080 return err;
7081
7082 err = add_ca0132_alt_eq_presets(codec);
7083 if (err < 0)
7084 return err;
7085
7086 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7087 "Enable OutFX", 0);
7088 if (err < 0)
7089 return err;
7090
7091 err = add_fx_switch(codec, CRYSTAL_VOICE,
7092 "Enable InFX", 1);
7093 if (err < 0)
7094 return err;
7095
7096 num_sliders = OUT_EFFECTS_COUNT - 1;
7097 for (i = 0; i < num_sliders; i++) {
7098 err = ca0132_alt_add_effect_slider(codec,
7099 ca0132_effects[i].nid,
7100 ca0132_effects[i].name,
7101 ca0132_effects[i].direct);
7102 if (err < 0)
7103 return err;
7104 }
7105
7106 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7107 "X-Bass Crossover", EFX_DIR_OUT);
7108
7109 if (err < 0)
7110 return err;
7111 } else {
7112 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7113 "PlayEnhancement", 0);
7114 if (err < 0)
7115 return err;
7116
7117 err = add_fx_switch(codec, CRYSTAL_VOICE,
7118 "CrystalVoice", 1);
7119 if (err < 0)
7120 return err;
7121 }
7122 err = add_voicefx(codec);
7123 if (err < 0)
7124 return err;
7125
7126 /*
7127 * If the codec uses alt_functions, you need the enumerated controls
7128 * to select the new outputs and inputs, plus add the new mic boost
7129 * setting control.
7130 */
7131 if (ca0132_use_alt_functions(spec)) {
7132 err = ca0132_alt_add_output_enum(codec);
7133 if (err < 0)
7134 return err;
7135 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7136 if (err < 0)
7137 return err;
7138 err = ca0132_alt_add_front_full_range_switch(codec);
7139 if (err < 0)
7140 return err;
7141 err = ca0132_alt_add_rear_full_range_switch(codec);
7142 if (err < 0)
7143 return err;
7144 err = ca0132_alt_add_bass_redirection_crossover(codec);
7145 if (err < 0)
7146 return err;
7147 err = ca0132_alt_add_bass_redirection_switch(codec);
7148 if (err < 0)
7149 return err;
7150 err = ca0132_alt_add_mic_boost_enum(codec);
7151 if (err < 0)
7152 return err;
7153 /*
7154 * ZxR only has microphone input, there is no front panel
7155 * header on the card, and aux-in is handled by the DBPro board.
7156 */
7157 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7158 err = ca0132_alt_add_input_enum(codec);
7159 if (err < 0)
7160 return err;
7161 }
7162 }
7163
7164 switch (ca0132_quirk(spec)) {
7165 case QUIRK_AE5:
7166 case QUIRK_AE7:
7167 err = ae5_add_headphone_gain_enum(codec);
7168 if (err < 0)
7169 return err;
7170 err = ae5_add_sound_filter_enum(codec);
7171 if (err < 0)
7172 return err;
7173 break;
7174 case QUIRK_ZXR:
7175 err = zxr_add_headphone_gain_switch(codec);
7176 if (err < 0)
7177 return err;
7178 break;
7179 default:
7180 break;
7181 }
7182
7183 #ifdef ENABLE_TUNING_CONTROLS
7184 add_tuning_ctls(codec);
7185 #endif
7186
7187 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7188 if (err < 0)
7189 return err;
7190
7191 if (spec->dig_out) {
7192 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7193 spec->dig_out);
7194 if (err < 0)
7195 return err;
7196 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7197 if (err < 0)
7198 return err;
7199 /* spec->multiout.share_spdif = 1; */
7200 }
7201
7202 if (spec->dig_in) {
7203 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7204 if (err < 0)
7205 return err;
7206 }
7207
7208 if (ca0132_use_alt_functions(spec))
7209 ca0132_alt_add_chmap_ctls(codec);
7210
7211 return 0;
7212 }
7213
dbpro_build_controls(struct hda_codec * codec)7214 static int dbpro_build_controls(struct hda_codec *codec)
7215 {
7216 struct ca0132_spec *spec = codec->spec;
7217 int err = 0;
7218
7219 if (spec->dig_out) {
7220 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7221 spec->dig_out);
7222 if (err < 0)
7223 return err;
7224 }
7225
7226 if (spec->dig_in) {
7227 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7228 if (err < 0)
7229 return err;
7230 }
7231
7232 return 0;
7233 }
7234
7235 /*
7236 * PCM
7237 */
7238 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7239 .substreams = 1,
7240 .channels_min = 2,
7241 .channels_max = 6,
7242 .ops = {
7243 .prepare = ca0132_playback_pcm_prepare,
7244 .cleanup = ca0132_playback_pcm_cleanup,
7245 .get_delay = ca0132_playback_pcm_delay,
7246 },
7247 };
7248
7249 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7250 .substreams = 1,
7251 .channels_min = 2,
7252 .channels_max = 2,
7253 .ops = {
7254 .prepare = ca0132_capture_pcm_prepare,
7255 .cleanup = ca0132_capture_pcm_cleanup,
7256 .get_delay = ca0132_capture_pcm_delay,
7257 },
7258 };
7259
7260 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7261 .substreams = 1,
7262 .channels_min = 2,
7263 .channels_max = 2,
7264 .ops = {
7265 .open = ca0132_dig_playback_pcm_open,
7266 .close = ca0132_dig_playback_pcm_close,
7267 .prepare = ca0132_dig_playback_pcm_prepare,
7268 .cleanup = ca0132_dig_playback_pcm_cleanup
7269 },
7270 };
7271
7272 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7273 .substreams = 1,
7274 .channels_min = 2,
7275 .channels_max = 2,
7276 };
7277
ca0132_build_pcms(struct hda_codec * codec)7278 static int ca0132_build_pcms(struct hda_codec *codec)
7279 {
7280 struct ca0132_spec *spec = codec->spec;
7281 struct hda_pcm *info;
7282
7283 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7284 if (!info)
7285 return -ENOMEM;
7286 if (ca0132_use_alt_functions(spec)) {
7287 info->own_chmap = true;
7288 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7289 = ca0132_alt_chmaps;
7290 }
7291 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7292 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7293 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7294 spec->multiout.max_channels;
7295 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7296 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7297 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7298
7299 /* With the DSP enabled, desktops don't use this ADC. */
7300 if (!ca0132_use_alt_functions(spec)) {
7301 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7302 if (!info)
7303 return -ENOMEM;
7304 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7305 ca0132_pcm_analog_capture;
7306 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7307 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7308 }
7309
7310 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7311 if (!info)
7312 return -ENOMEM;
7313 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7314 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7315 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7316
7317 if (!spec->dig_out && !spec->dig_in)
7318 return 0;
7319
7320 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7321 if (!info)
7322 return -ENOMEM;
7323 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7324 if (spec->dig_out) {
7325 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7326 ca0132_pcm_digital_playback;
7327 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7328 }
7329 if (spec->dig_in) {
7330 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7331 ca0132_pcm_digital_capture;
7332 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7333 }
7334
7335 return 0;
7336 }
7337
dbpro_build_pcms(struct hda_codec * codec)7338 static int dbpro_build_pcms(struct hda_codec *codec)
7339 {
7340 struct ca0132_spec *spec = codec->spec;
7341 struct hda_pcm *info;
7342
7343 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7344 if (!info)
7345 return -ENOMEM;
7346 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7347 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7348 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7349
7350
7351 if (!spec->dig_out && !spec->dig_in)
7352 return 0;
7353
7354 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7355 if (!info)
7356 return -ENOMEM;
7357 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7358 if (spec->dig_out) {
7359 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7360 ca0132_pcm_digital_playback;
7361 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7362 }
7363 if (spec->dig_in) {
7364 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7365 ca0132_pcm_digital_capture;
7366 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7367 }
7368
7369 return 0;
7370 }
7371
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)7372 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7373 {
7374 if (pin) {
7375 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7376 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7377 snd_hda_codec_write(codec, pin, 0,
7378 AC_VERB_SET_AMP_GAIN_MUTE,
7379 AMP_OUT_UNMUTE);
7380 }
7381 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7382 snd_hda_codec_write(codec, dac, 0,
7383 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7384 }
7385
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)7386 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7387 {
7388 if (pin) {
7389 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7390 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7391 snd_hda_codec_write(codec, pin, 0,
7392 AC_VERB_SET_AMP_GAIN_MUTE,
7393 AMP_IN_UNMUTE(0));
7394 }
7395 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7396 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7397 AMP_IN_UNMUTE(0));
7398
7399 /* init to 0 dB and unmute. */
7400 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7401 HDA_AMP_VOLMASK, 0x5a);
7402 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7403 HDA_AMP_MUTE, 0);
7404 }
7405 }
7406
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)7407 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7408 {
7409 unsigned int caps;
7410
7411 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7412 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7413 snd_hda_override_amp_caps(codec, nid, dir, caps);
7414 }
7415
7416 /*
7417 * Switch between Digital built-in mic and analog mic.
7418 */
ca0132_set_dmic(struct hda_codec * codec,int enable)7419 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7420 {
7421 struct ca0132_spec *spec = codec->spec;
7422 unsigned int tmp;
7423 u8 val;
7424 unsigned int oldval;
7425
7426 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7427
7428 oldval = stop_mic1(codec);
7429 ca0132_set_vipsource(codec, 0);
7430 if (enable) {
7431 /* set DMic input as 2-ch */
7432 tmp = FLOAT_TWO;
7433 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7434
7435 val = spec->dmic_ctl;
7436 val |= 0x80;
7437 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7438 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7439
7440 if (!(spec->dmic_ctl & 0x20))
7441 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7442 } else {
7443 /* set AMic input as mono */
7444 tmp = FLOAT_ONE;
7445 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7446
7447 val = spec->dmic_ctl;
7448 /* clear bit7 and bit5 to disable dmic */
7449 val &= 0x5f;
7450 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7451 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7452
7453 if (!(spec->dmic_ctl & 0x20))
7454 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7455 }
7456 ca0132_set_vipsource(codec, 1);
7457 resume_mic1(codec, oldval);
7458 }
7459
7460 /*
7461 * Initialization for Digital Mic.
7462 */
ca0132_init_dmic(struct hda_codec * codec)7463 static void ca0132_init_dmic(struct hda_codec *codec)
7464 {
7465 struct ca0132_spec *spec = codec->spec;
7466 u8 val;
7467
7468 /* Setup Digital Mic here, but don't enable.
7469 * Enable based on jack detect.
7470 */
7471
7472 /* MCLK uses MPIO1, set to enable.
7473 * Bit 2-0: MPIO select
7474 * Bit 3: set to disable
7475 * Bit 7-4: reserved
7476 */
7477 val = 0x01;
7478 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7479 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7480
7481 /* Data1 uses MPIO3. Data2 not use
7482 * Bit 2-0: Data1 MPIO select
7483 * Bit 3: set disable Data1
7484 * Bit 6-4: Data2 MPIO select
7485 * Bit 7: set disable Data2
7486 */
7487 val = 0x83;
7488 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7489 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7490
7491 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7492 * Bit 3-0: Channel mask
7493 * Bit 4: set for 48KHz, clear for 32KHz
7494 * Bit 5: mode
7495 * Bit 6: set to select Data2, clear for Data1
7496 * Bit 7: set to enable DMic, clear for AMic
7497 */
7498 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7499 val = 0x33;
7500 else
7501 val = 0x23;
7502 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7503 spec->dmic_ctl = val;
7504 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7505 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7506 }
7507
7508 /*
7509 * Initialization for Analog Mic 2
7510 */
ca0132_init_analog_mic2(struct hda_codec * codec)7511 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7512 {
7513 struct ca0132_spec *spec = codec->spec;
7514
7515 mutex_lock(&spec->chipio_mutex);
7516
7517 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7518 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7519
7520 mutex_unlock(&spec->chipio_mutex);
7521 }
7522
ca0132_refresh_widget_caps(struct hda_codec * codec)7523 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7524 {
7525 struct ca0132_spec *spec = codec->spec;
7526 int i;
7527
7528 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7529 snd_hda_codec_update_widgets(codec);
7530
7531 for (i = 0; i < spec->multiout.num_dacs; i++)
7532 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7533
7534 for (i = 0; i < spec->num_outputs; i++)
7535 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7536
7537 for (i = 0; i < spec->num_inputs; i++) {
7538 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7539 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7540 }
7541 }
7542
7543
7544 /* If there is an active channel for some reason, find it and free it. */
ca0132_alt_free_active_dma_channels(struct hda_codec * codec)7545 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7546 {
7547 unsigned int i, tmp;
7548 int status;
7549
7550 /* Read active DSPDMAC channel register. */
7551 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7552 if (status >= 0) {
7553 /* AND against 0xfff to get the active channel bits. */
7554 tmp = tmp & 0xfff;
7555
7556 /* If there are no active channels, nothing to free. */
7557 if (!tmp)
7558 return;
7559 } else {
7560 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7561 __func__);
7562 return;
7563 }
7564
7565 /*
7566 * Check each DSP DMA channel for activity, and if the channel is
7567 * active, free it.
7568 */
7569 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7570 if (dsp_is_dma_active(codec, i)) {
7571 status = dspio_free_dma_chan(codec, i);
7572 if (status < 0)
7573 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7574 __func__, i);
7575 }
7576 }
7577 }
7578
7579 /*
7580 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7581 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7582 * Instead, audio is now routed through the DSP's DMA controllers, which
7583 * the DSP is tasked with setting up itself. Through debugging, it seems the
7584 * cause of most of the no-audio on startup issues were due to improperly
7585 * configured DSP DMA channels.
7586 *
7587 * Normally, the DSP configures these the first time an HDA audio stream is
7588 * started post DSP firmware download. That is why creating a 'dummy' stream
7589 * worked in fixing the audio in some cases. This works most of the time, but
7590 * sometimes if a stream is started/stopped before the DSP can setup the DMA
7591 * configuration registers, it ends up in a broken state. Issues can also
7592 * arise if streams are started in an unusual order, i.e the audio output dma
7593 * channel being sandwiched between the mic1 and mic2 dma channels.
7594 *
7595 * The solution to this is to make sure that the DSP has no DMA channels
7596 * in use post DSP firmware download, and then to manually start each default
7597 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7598 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7599 */
ca0132_alt_start_dsp_audio_streams(struct hda_codec * codec)7600 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7601 {
7602 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7603 struct ca0132_spec *spec = codec->spec;
7604 unsigned int i, tmp;
7605
7606 /*
7607 * Check if any of the default streams are active, and if they are,
7608 * stop them.
7609 */
7610 mutex_lock(&spec->chipio_mutex);
7611
7612 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7613 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7614
7615 if (tmp) {
7616 chipio_set_stream_control(codec,
7617 dsp_dma_stream_ids[i], 0);
7618 }
7619 }
7620
7621 mutex_unlock(&spec->chipio_mutex);
7622
7623 /*
7624 * If all DSP streams are inactive, there should be no active DSP DMA
7625 * channels. Check and make sure this is the case, and if it isn't,
7626 * free any active channels.
7627 */
7628 ca0132_alt_free_active_dma_channels(codec);
7629
7630 mutex_lock(&spec->chipio_mutex);
7631
7632 /* Make sure stream 0x0c is six channels. */
7633 chipio_set_stream_channels(codec, 0x0c, 6);
7634
7635 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7636 chipio_set_stream_control(codec,
7637 dsp_dma_stream_ids[i], 1);
7638
7639 /* Give the DSP some time to setup the DMA channel. */
7640 msleep(75);
7641 }
7642
7643 mutex_unlock(&spec->chipio_mutex);
7644 }
7645
7646 /*
7647 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7648 * router', where each entry represents a 48khz audio channel, with a format
7649 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7650 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7651 * and 3 if it's using Sample Rate Converter ports.
7652 * An example is:
7653 * 0x0001f8c0
7654 * In this case, f8 is the destination, and c0 is the source. The number value
7655 * is 1.
7656 * This region of memory is normally managed internally by the 8051, where
7657 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7658 * entry within the 0x190000 range, and when a range of entries is in use, the
7659 * ending value is overwritten with 0xff.
7660 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7661 * streamID's, where each entry is a starting 0x190000 port offset.
7662 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7663 * offset for the corresponding streamID.
7664 *
7665 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7666 * the 8051, then manually overwritten to remap the ports to work with the
7667 * new DACs.
7668 *
7669 * Currently known portID's:
7670 * 0x00-0x1f: HDA audio stream input/output ports.
7671 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7672 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7673 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7674 * 0xe0-0xff: DAC/ADC audio input/output ports.
7675 *
7676 * Currently known streamID's:
7677 * 0x03: Mic1 ADC to DSP.
7678 * 0x04: Mic2 ADC to DSP.
7679 * 0x05: HDA node 0x02 audio stream to DSP.
7680 * 0x0f: DSP Mic exit to HDA node 0x07.
7681 * 0x0c: DSP processed audio to DACs.
7682 * 0x14: DAC0, front L/R.
7683 *
7684 * It is possible to route the HDA audio streams directly to the DAC and
7685 * bypass the DSP entirely, with the only downside being that since the DSP
7686 * does volume control, the only volume control you'll get is through PCM on
7687 * the PC side, in the same way volume is handled for optical out. This may be
7688 * useful for debugging.
7689 */
chipio_remap_stream(struct hda_codec * codec,const struct chipio_stream_remap_data * remap_data)7690 static void chipio_remap_stream(struct hda_codec *codec,
7691 const struct chipio_stream_remap_data *remap_data)
7692 {
7693 unsigned int i, stream_offset;
7694
7695 /* Get the starting port for the stream to be remapped. */
7696 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7697 &stream_offset);
7698
7699 /*
7700 * Check if the stream's port value is 0xff, because the 8051 may not
7701 * have gotten around to setting up the stream yet. Wait until it's
7702 * setup to remap it's ports.
7703 */
7704 if (stream_offset == 0xff) {
7705 for (i = 0; i < 5; i++) {
7706 msleep(25);
7707
7708 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7709 &stream_offset);
7710
7711 if (stream_offset != 0xff)
7712 break;
7713 }
7714 }
7715
7716 if (stream_offset == 0xff) {
7717 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7718 __func__, remap_data->stream_id);
7719 return;
7720 }
7721
7722 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7723 stream_offset *= 0x04;
7724 stream_offset += 0x190000;
7725
7726 for (i = 0; i < remap_data->count; i++) {
7727 chipio_write_no_mutex(codec,
7728 stream_offset + remap_data->offset[i],
7729 remap_data->value[i]);
7730 }
7731
7732 /* Update stream map configuration. */
7733 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7734 }
7735
7736 /*
7737 * Default speaker tuning values setup for alternative codecs.
7738 */
7739 static const unsigned int sbz_default_delay_values[] = {
7740 /* Non-zero values are floating point 0.000198. */
7741 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7742 };
7743
7744 static const unsigned int zxr_default_delay_values[] = {
7745 /* Non-zero values are floating point 0.000220. */
7746 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7747 };
7748
7749 static const unsigned int ae5_default_delay_values[] = {
7750 /* Non-zero values are floating point 0.000100. */
7751 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7752 };
7753
7754 /*
7755 * If we never change these, probably only need them on initialization.
7756 */
ca0132_alt_init_speaker_tuning(struct hda_codec * codec)7757 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7758 {
7759 struct ca0132_spec *spec = codec->spec;
7760 unsigned int i, tmp, start_req, end_req;
7761 const unsigned int *values;
7762
7763 switch (ca0132_quirk(spec)) {
7764 case QUIRK_SBZ:
7765 values = sbz_default_delay_values;
7766 break;
7767 case QUIRK_ZXR:
7768 values = zxr_default_delay_values;
7769 break;
7770 case QUIRK_AE5:
7771 case QUIRK_AE7:
7772 values = ae5_default_delay_values;
7773 break;
7774 default:
7775 values = sbz_default_delay_values;
7776 break;
7777 }
7778
7779 tmp = FLOAT_ZERO;
7780 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7781
7782 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7783 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7784 for (i = start_req; i < end_req + 1; i++)
7785 dspio_set_uint_param(codec, 0x96, i, tmp);
7786
7787 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7788 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7789 for (i = start_req; i < end_req + 1; i++)
7790 dspio_set_uint_param(codec, 0x96, i, tmp);
7791
7792
7793 for (i = 0; i < 6; i++)
7794 dspio_set_uint_param(codec, 0x96,
7795 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7796 }
7797
7798 /*
7799 * Initialize mic for non-chromebook ca0132 implementations.
7800 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)7801 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7802 {
7803 struct ca0132_spec *spec = codec->spec;
7804 unsigned int tmp;
7805
7806 /* Mic 1 Setup */
7807 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7808 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7809 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7810 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7811 tmp = FLOAT_ONE;
7812 } else
7813 tmp = FLOAT_THREE;
7814 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7815
7816 /* Mic 2 setup (not present on desktop cards) */
7817 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7818 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7819 if (ca0132_quirk(spec) == QUIRK_R3DI)
7820 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7821 tmp = FLOAT_ZERO;
7822 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7823 }
7824
7825 /*
7826 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7827 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7828 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7829 * having an updated DAC, which changes the destination to that DAC.
7830 */
sbz_connect_streams(struct hda_codec * codec)7831 static void sbz_connect_streams(struct hda_codec *codec)
7832 {
7833 struct ca0132_spec *spec = codec->spec;
7834
7835 mutex_lock(&spec->chipio_mutex);
7836
7837 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7838
7839 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7840 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7841
7842 /* Setup stream 0x14 with it's source and destination points */
7843 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7844 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7845 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7846 chipio_set_stream_channels(codec, 0x14, 2);
7847 chipio_set_stream_control(codec, 0x14, 1);
7848
7849 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7850
7851 mutex_unlock(&spec->chipio_mutex);
7852 }
7853
7854 /*
7855 * Write data through ChipIO to setup proper stream destinations.
7856 * Not sure how it exactly works, but it seems to direct data
7857 * to different destinations. Example is f8 to c0, e0 to c0.
7858 * All I know is, if you don't set these, you get no sound.
7859 */
sbz_chipio_startup_data(struct hda_codec * codec)7860 static void sbz_chipio_startup_data(struct hda_codec *codec)
7861 {
7862 const struct chipio_stream_remap_data *dsp_out_remap_data;
7863 struct ca0132_spec *spec = codec->spec;
7864
7865 mutex_lock(&spec->chipio_mutex);
7866 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7867
7868 /* Remap DAC0's output ports. */
7869 chipio_remap_stream(codec, &stream_remap_data[0]);
7870
7871 /* Remap DSP audio output stream ports. */
7872 switch (ca0132_quirk(spec)) {
7873 case QUIRK_SBZ:
7874 dsp_out_remap_data = &stream_remap_data[1];
7875 break;
7876
7877 case QUIRK_ZXR:
7878 dsp_out_remap_data = &stream_remap_data[2];
7879 break;
7880
7881 default:
7882 dsp_out_remap_data = NULL;
7883 break;
7884 }
7885
7886 if (dsp_out_remap_data)
7887 chipio_remap_stream(codec, dsp_out_remap_data);
7888
7889 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7890 mutex_unlock(&spec->chipio_mutex);
7891 }
7892
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7893 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7894 {
7895 struct ca0132_spec *spec = codec->spec;
7896 unsigned int tmp;
7897
7898 chipio_set_stream_control(codec, 0x03, 0);
7899 chipio_set_stream_control(codec, 0x04, 0);
7900
7901 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7902 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7903
7904 tmp = FLOAT_THREE;
7905 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7906
7907 chipio_set_stream_control(codec, 0x03, 1);
7908 chipio_set_stream_control(codec, 0x04, 1);
7909
7910 switch (ca0132_quirk(spec)) {
7911 case QUIRK_SBZ:
7912 chipio_write(codec, 0x18b098, 0x0000000c);
7913 chipio_write(codec, 0x18b09C, 0x0000000c);
7914 break;
7915 case QUIRK_AE5:
7916 chipio_write(codec, 0x18b098, 0x0000000c);
7917 chipio_write(codec, 0x18b09c, 0x0000004c);
7918 break;
7919 default:
7920 break;
7921 }
7922 }
7923
ae5_post_dsp_register_set(struct hda_codec * codec)7924 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7925 {
7926 struct ca0132_spec *spec = codec->spec;
7927
7928 chipio_8051_write_direct(codec, 0x93, 0x10);
7929 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7930
7931 writeb(0xff, spec->mem_base + 0x304);
7932 writeb(0xff, spec->mem_base + 0x304);
7933 writeb(0xff, spec->mem_base + 0x304);
7934 writeb(0xff, spec->mem_base + 0x304);
7935 writeb(0x00, spec->mem_base + 0x100);
7936 writeb(0xff, spec->mem_base + 0x304);
7937 writeb(0x00, spec->mem_base + 0x100);
7938 writeb(0xff, spec->mem_base + 0x304);
7939 writeb(0x00, spec->mem_base + 0x100);
7940 writeb(0xff, spec->mem_base + 0x304);
7941 writeb(0x00, spec->mem_base + 0x100);
7942 writeb(0xff, spec->mem_base + 0x304);
7943
7944 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7945 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7946 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7947 }
7948
ae5_post_dsp_param_setup(struct hda_codec * codec)7949 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7950 {
7951 /*
7952 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7953 * which seems to be 'multichannel'. This is also mentioned in the
7954 * AE-5's registry values in Windows.
7955 */
7956 chipio_set_control_param(codec, 3, 0);
7957 /*
7958 * I believe ASI is 'audio serial interface' and that it's used to
7959 * change colors on the external LED strip connected to the AE-5.
7960 */
7961 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7962
7963 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7964 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7965
7966 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7967 }
7968
ae5_post_dsp_pll_setup(struct hda_codec * codec)7969 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7970 {
7971 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7972 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7973 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7974 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7975 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7976 }
7977
ae5_post_dsp_stream_setup(struct hda_codec * codec)7978 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7979 {
7980 struct ca0132_spec *spec = codec->spec;
7981
7982 mutex_lock(&spec->chipio_mutex);
7983
7984 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7985
7986 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7987
7988 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7989
7990 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7991 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7992 chipio_set_stream_channels(codec, 0x18, 6);
7993 chipio_set_stream_control(codec, 0x18, 1);
7994
7995 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7996
7997 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7998
7999 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
8000
8001 mutex_unlock(&spec->chipio_mutex);
8002 }
8003
ae5_post_dsp_startup_data(struct hda_codec * codec)8004 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8005 {
8006 struct ca0132_spec *spec = codec->spec;
8007
8008 mutex_lock(&spec->chipio_mutex);
8009
8010 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8011 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8012 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8013 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8014
8015 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8016 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8017 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8018 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8019 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8020 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8021 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8022 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8023 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8024 ca0113_mmio_gpio_set(codec, 0, true);
8025 ca0113_mmio_gpio_set(codec, 1, true);
8026 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8027
8028 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8029
8030 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8031 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8032
8033 mutex_unlock(&spec->chipio_mutex);
8034 }
8035
ae7_post_dsp_setup_ports(struct hda_codec * codec)8036 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8037 {
8038 struct ca0132_spec *spec = codec->spec;
8039
8040 mutex_lock(&spec->chipio_mutex);
8041
8042 /* Seems to share the same port remapping as the SBZ. */
8043 chipio_remap_stream(codec, &stream_remap_data[1]);
8044
8045 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8046 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8047 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8048 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8049 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8050 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8051 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8052 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8053
8054 mutex_unlock(&spec->chipio_mutex);
8055 }
8056
ae7_post_dsp_asi_stream_setup(struct hda_codec * codec)8057 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8058 {
8059 struct ca0132_spec *spec = codec->spec;
8060
8061 mutex_lock(&spec->chipio_mutex);
8062
8063 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8064 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8065
8066 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8067
8068 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8069 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8070
8071 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8072 chipio_set_stream_channels(codec, 0x18, 6);
8073 chipio_set_stream_control(codec, 0x18, 1);
8074
8075 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8076
8077 mutex_unlock(&spec->chipio_mutex);
8078 }
8079
ae7_post_dsp_pll_setup(struct hda_codec * codec)8080 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8081 {
8082 static const unsigned int addr[] = {
8083 0x41, 0x45, 0x40, 0x43, 0x51
8084 };
8085 static const unsigned int data[] = {
8086 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8087 };
8088 unsigned int i;
8089
8090 for (i = 0; i < ARRAY_SIZE(addr); i++)
8091 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8092 }
8093
ae7_post_dsp_asi_setup_ports(struct hda_codec * codec)8094 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8095 {
8096 struct ca0132_spec *spec = codec->spec;
8097 static const unsigned int target[] = {
8098 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8099 };
8100 static const unsigned int data[] = {
8101 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8102 };
8103 unsigned int i;
8104
8105 mutex_lock(&spec->chipio_mutex);
8106
8107 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8108
8109 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8110 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8111 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8112 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8113
8114 ae7_post_dsp_pll_setup(codec);
8115 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8116
8117 for (i = 0; i < ARRAY_SIZE(target); i++)
8118 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8119
8120 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8121 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8122 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8123
8124 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8125 chipio_set_stream_channels(codec, 0x21, 2);
8126 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8127
8128 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8129 /*
8130 * In the 8051's memory, this param is referred to as 'n2sid', which I
8131 * believe is 'node to streamID'. It seems to be a way to assign a
8132 * stream to a given HDA node.
8133 */
8134 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8135
8136 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8137
8138 /*
8139 * Now, at this point on Windows, an actual stream is setup and
8140 * seemingly sends data to the HDA node 0x09, which is the digital
8141 * audio input node. This is left out here, because obviously I don't
8142 * know what data is being sent. Interestingly, the AE-5 seems to go
8143 * through the motions of getting here and never actually takes this
8144 * step, but the AE-7 does.
8145 */
8146
8147 ca0113_mmio_gpio_set(codec, 0, 1);
8148 ca0113_mmio_gpio_set(codec, 1, 1);
8149
8150 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8151 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8152 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8153 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8154
8155 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8156 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8157
8158 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8159 chipio_set_stream_channels(codec, 0x18, 6);
8160
8161 /*
8162 * Runs again, this has been repeated a few times, but I'm just
8163 * following what the Windows driver does.
8164 */
8165 ae7_post_dsp_pll_setup(codec);
8166 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8167
8168 mutex_unlock(&spec->chipio_mutex);
8169 }
8170
8171 /*
8172 * The Windows driver has commands that seem to setup ASI, which I believe to
8173 * be some sort of audio serial interface. My current speculation is that it's
8174 * related to communicating with the new DAC.
8175 */
ae7_post_dsp_asi_setup(struct hda_codec * codec)8176 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8177 {
8178 chipio_8051_write_direct(codec, 0x93, 0x10);
8179
8180 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8181
8182 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8183 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8184
8185 chipio_set_control_param(codec, 3, 3);
8186 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8187
8188 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8189 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8190 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8191
8192 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8193
8194 ae7_post_dsp_pll_setup(codec);
8195 ae7_post_dsp_asi_stream_setup(codec);
8196
8197 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8198
8199 ae7_post_dsp_asi_setup_ports(codec);
8200 }
8201
8202 /*
8203 * Setup default parameters for DSP
8204 */
ca0132_setup_defaults(struct hda_codec * codec)8205 static void ca0132_setup_defaults(struct hda_codec *codec)
8206 {
8207 struct ca0132_spec *spec = codec->spec;
8208 unsigned int tmp;
8209 int num_fx;
8210 int idx, i;
8211
8212 if (spec->dsp_state != DSP_DOWNLOADED)
8213 return;
8214
8215 /* out, in effects + voicefx */
8216 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8217 for (idx = 0; idx < num_fx; idx++) {
8218 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8219 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8220 ca0132_effects[idx].reqs[i],
8221 ca0132_effects[idx].def_vals[i]);
8222 }
8223 }
8224
8225 /*remove DSP headroom*/
8226 tmp = FLOAT_ZERO;
8227 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8228
8229 /*set speaker EQ bypass attenuation*/
8230 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8231
8232 /* set AMic1 and AMic2 as mono mic */
8233 tmp = FLOAT_ONE;
8234 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8235 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8236
8237 /* set AMic1 as CrystalVoice input */
8238 tmp = FLOAT_ONE;
8239 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8240
8241 /* set WUH source */
8242 tmp = FLOAT_TWO;
8243 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8244 }
8245
8246 /*
8247 * Setup default parameters for Recon3D/Recon3Di DSP.
8248 */
8249
r3d_setup_defaults(struct hda_codec * codec)8250 static void r3d_setup_defaults(struct hda_codec *codec)
8251 {
8252 struct ca0132_spec *spec = codec->spec;
8253 unsigned int tmp;
8254 int num_fx;
8255 int idx, i;
8256
8257 if (spec->dsp_state != DSP_DOWNLOADED)
8258 return;
8259
8260 ca0132_alt_init_analog_mics(codec);
8261 ca0132_alt_start_dsp_audio_streams(codec);
8262
8263 /*remove DSP headroom*/
8264 tmp = FLOAT_ZERO;
8265 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8266
8267 /* set WUH source */
8268 tmp = FLOAT_TWO;
8269 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8270 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8271
8272 /* Set speaker source? */
8273 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8274
8275 if (ca0132_quirk(spec) == QUIRK_R3DI)
8276 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8277
8278 /* Disable mute on Center/LFE. */
8279 if (ca0132_quirk(spec) == QUIRK_R3D) {
8280 ca0113_mmio_gpio_set(codec, 2, false);
8281 ca0113_mmio_gpio_set(codec, 4, true);
8282 }
8283
8284 /* Setup effect defaults */
8285 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8286 for (idx = 0; idx < num_fx; idx++) {
8287 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8288 dspio_set_uint_param(codec,
8289 ca0132_effects[idx].mid,
8290 ca0132_effects[idx].reqs[i],
8291 ca0132_effects[idx].def_vals[i]);
8292 }
8293 }
8294 }
8295
8296 /*
8297 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8298 * than the Chromebook setup.
8299 */
sbz_setup_defaults(struct hda_codec * codec)8300 static void sbz_setup_defaults(struct hda_codec *codec)
8301 {
8302 struct ca0132_spec *spec = codec->spec;
8303 unsigned int tmp;
8304 int num_fx;
8305 int idx, i;
8306
8307 if (spec->dsp_state != DSP_DOWNLOADED)
8308 return;
8309
8310 ca0132_alt_init_analog_mics(codec);
8311 ca0132_alt_start_dsp_audio_streams(codec);
8312 sbz_connect_streams(codec);
8313 sbz_chipio_startup_data(codec);
8314
8315 /*
8316 * Sets internal input loopback to off, used to have a switch to
8317 * enable input loopback, but turned out to be way too buggy.
8318 */
8319 tmp = FLOAT_ONE;
8320 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8321 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8322
8323 /*remove DSP headroom*/
8324 tmp = FLOAT_ZERO;
8325 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8326
8327 /* set WUH source */
8328 tmp = FLOAT_TWO;
8329 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8330 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8331
8332 /* Set speaker source? */
8333 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8334
8335 ca0132_alt_dsp_initial_mic_setup(codec);
8336
8337 /* out, in effects + voicefx */
8338 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8339 for (idx = 0; idx < num_fx; idx++) {
8340 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8341 dspio_set_uint_param(codec,
8342 ca0132_effects[idx].mid,
8343 ca0132_effects[idx].reqs[i],
8344 ca0132_effects[idx].def_vals[i]);
8345 }
8346 }
8347
8348 ca0132_alt_init_speaker_tuning(codec);
8349 }
8350
8351 /*
8352 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8353 */
ae5_setup_defaults(struct hda_codec * codec)8354 static void ae5_setup_defaults(struct hda_codec *codec)
8355 {
8356 struct ca0132_spec *spec = codec->spec;
8357 unsigned int tmp;
8358 int num_fx;
8359 int idx, i;
8360
8361 if (spec->dsp_state != DSP_DOWNLOADED)
8362 return;
8363
8364 ca0132_alt_init_analog_mics(codec);
8365 ca0132_alt_start_dsp_audio_streams(codec);
8366
8367 /* New, unknown SCP req's */
8368 tmp = FLOAT_ZERO;
8369 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8370 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8371 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8372 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8373
8374 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8375 ca0113_mmio_gpio_set(codec, 0, false);
8376 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8377
8378 /* Internal loopback off */
8379 tmp = FLOAT_ONE;
8380 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8381 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8382
8383 /*remove DSP headroom*/
8384 tmp = FLOAT_ZERO;
8385 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8386
8387 /* set WUH source */
8388 tmp = FLOAT_TWO;
8389 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8390 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8391
8392 /* Set speaker source? */
8393 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8394
8395 ca0132_alt_dsp_initial_mic_setup(codec);
8396 ae5_post_dsp_register_set(codec);
8397 ae5_post_dsp_param_setup(codec);
8398 ae5_post_dsp_pll_setup(codec);
8399 ae5_post_dsp_stream_setup(codec);
8400 ae5_post_dsp_startup_data(codec);
8401
8402 /* out, in effects + voicefx */
8403 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8404 for (idx = 0; idx < num_fx; idx++) {
8405 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8406 dspio_set_uint_param(codec,
8407 ca0132_effects[idx].mid,
8408 ca0132_effects[idx].reqs[i],
8409 ca0132_effects[idx].def_vals[i]);
8410 }
8411 }
8412
8413 ca0132_alt_init_speaker_tuning(codec);
8414 }
8415
8416 /*
8417 * Setup default parameters for the Sound Blaster AE-7 DSP.
8418 */
ae7_setup_defaults(struct hda_codec * codec)8419 static void ae7_setup_defaults(struct hda_codec *codec)
8420 {
8421 struct ca0132_spec *spec = codec->spec;
8422 unsigned int tmp;
8423 int num_fx;
8424 int idx, i;
8425
8426 if (spec->dsp_state != DSP_DOWNLOADED)
8427 return;
8428
8429 ca0132_alt_init_analog_mics(codec);
8430 ca0132_alt_start_dsp_audio_streams(codec);
8431 ae7_post_dsp_setup_ports(codec);
8432
8433 tmp = FLOAT_ZERO;
8434 dspio_set_uint_param(codec, 0x96,
8435 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8436 dspio_set_uint_param(codec, 0x96,
8437 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8438
8439 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8440
8441 /* New, unknown SCP req's */
8442 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8443 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8444
8445 ca0113_mmio_gpio_set(codec, 0, false);
8446
8447 /* Internal loopback off */
8448 tmp = FLOAT_ONE;
8449 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8450 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8451
8452 /*remove DSP headroom*/
8453 tmp = FLOAT_ZERO;
8454 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8455
8456 /* set WUH source */
8457 tmp = FLOAT_TWO;
8458 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8459 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8460
8461 /* Set speaker source? */
8462 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8463 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8464
8465 /*
8466 * This is the second time we've called this, but this is seemingly
8467 * what Windows does.
8468 */
8469 ca0132_alt_init_analog_mics(codec);
8470
8471 ae7_post_dsp_asi_setup(codec);
8472
8473 /*
8474 * Not sure why, but these are both set to 1. They're only set to 0
8475 * upon shutdown.
8476 */
8477 ca0113_mmio_gpio_set(codec, 0, true);
8478 ca0113_mmio_gpio_set(codec, 1, true);
8479
8480 /* Volume control related. */
8481 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8482 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8483 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8484
8485 /* out, in effects + voicefx */
8486 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8487 for (idx = 0; idx < num_fx; idx++) {
8488 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8489 dspio_set_uint_param(codec,
8490 ca0132_effects[idx].mid,
8491 ca0132_effects[idx].reqs[i],
8492 ca0132_effects[idx].def_vals[i]);
8493 }
8494 }
8495
8496 ca0132_alt_init_speaker_tuning(codec);
8497 }
8498
8499 /*
8500 * Initialization of flags in chip
8501 */
ca0132_init_flags(struct hda_codec * codec)8502 static void ca0132_init_flags(struct hda_codec *codec)
8503 {
8504 struct ca0132_spec *spec = codec->spec;
8505
8506 if (ca0132_use_alt_functions(spec)) {
8507 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8508 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8509 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8510 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8511 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8512 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8513 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8514 chipio_set_control_flag(codec,
8515 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8516 chipio_set_control_flag(codec,
8517 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8518 } else {
8519 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8520 chipio_set_control_flag(codec,
8521 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8522 chipio_set_control_flag(codec,
8523 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8524 chipio_set_control_flag(codec,
8525 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8526 chipio_set_control_flag(codec,
8527 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8528 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8529 }
8530 }
8531
8532 /*
8533 * Initialization of parameters in chip
8534 */
ca0132_init_params(struct hda_codec * codec)8535 static void ca0132_init_params(struct hda_codec *codec)
8536 {
8537 struct ca0132_spec *spec = codec->spec;
8538
8539 if (ca0132_use_alt_functions(spec)) {
8540 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8541 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8542 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8543 chipio_set_control_param(codec, 0, 0);
8544 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8545 }
8546
8547 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8548 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8549 }
8550
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)8551 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8552 {
8553 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8554 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8555 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8556 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8557 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8558 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8559
8560 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8561 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8562 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8563 }
8564
ca0132_download_dsp_images(struct hda_codec * codec)8565 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8566 {
8567 bool dsp_loaded = false;
8568 struct ca0132_spec *spec = codec->spec;
8569 const struct dsp_image_seg *dsp_os_image;
8570 const struct firmware *fw_entry = NULL;
8571 /*
8572 * Alternate firmwares for different variants. The Recon3Di apparently
8573 * can use the default firmware, but I'll leave the option in case
8574 * it needs it again.
8575 */
8576 switch (ca0132_quirk(spec)) {
8577 case QUIRK_SBZ:
8578 case QUIRK_R3D:
8579 case QUIRK_AE5:
8580 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8581 codec->card->dev) != 0)
8582 codec_dbg(codec, "Desktop firmware not found.");
8583 else
8584 codec_dbg(codec, "Desktop firmware selected.");
8585 break;
8586 case QUIRK_R3DI:
8587 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8588 codec->card->dev) != 0)
8589 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8590 else
8591 codec_dbg(codec, "Recon3Di firmware selected.");
8592 break;
8593 default:
8594 break;
8595 }
8596 /*
8597 * Use default ctefx.bin if no alt firmware is detected, or if none
8598 * exists for your particular codec.
8599 */
8600 if (!fw_entry) {
8601 codec_dbg(codec, "Default firmware selected.");
8602 if (request_firmware(&fw_entry, EFX_FILE,
8603 codec->card->dev) != 0)
8604 return false;
8605 }
8606
8607 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8608 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8609 codec_err(codec, "ca0132 DSP load image failed\n");
8610 goto exit_download;
8611 }
8612
8613 dsp_loaded = dspload_wait_loaded(codec);
8614
8615 exit_download:
8616 release_firmware(fw_entry);
8617
8618 return dsp_loaded;
8619 }
8620
ca0132_download_dsp(struct hda_codec * codec)8621 static void ca0132_download_dsp(struct hda_codec *codec)
8622 {
8623 struct ca0132_spec *spec = codec->spec;
8624
8625 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8626 return; /* NOP */
8627 #endif
8628
8629 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8630 return; /* don't retry failures */
8631
8632 chipio_enable_clocks(codec);
8633 if (spec->dsp_state != DSP_DOWNLOADED) {
8634 spec->dsp_state = DSP_DOWNLOADING;
8635
8636 if (!ca0132_download_dsp_images(codec))
8637 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8638 else
8639 spec->dsp_state = DSP_DOWNLOADED;
8640 }
8641
8642 /* For codecs using alt functions, this is already done earlier */
8643 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8644 ca0132_set_dsp_msr(codec, true);
8645 }
8646
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)8647 static void ca0132_process_dsp_response(struct hda_codec *codec,
8648 struct hda_jack_callback *callback)
8649 {
8650 struct ca0132_spec *spec = codec->spec;
8651
8652 codec_dbg(codec, "ca0132_process_dsp_response\n");
8653 snd_hda_power_up_pm(codec);
8654 if (spec->wait_scp) {
8655 if (dspio_get_response_data(codec) >= 0)
8656 spec->wait_scp = 0;
8657 }
8658
8659 dspio_clear_response_queue(codec);
8660 snd_hda_power_down_pm(codec);
8661 }
8662
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8663 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8664 {
8665 struct ca0132_spec *spec = codec->spec;
8666 struct hda_jack_tbl *tbl;
8667
8668 /* Delay enabling the HP amp, to let the mic-detection
8669 * state machine run.
8670 */
8671 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8672 if (tbl)
8673 tbl->block_report = 1;
8674 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8675 }
8676
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8677 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8678 {
8679 struct ca0132_spec *spec = codec->spec;
8680
8681 if (ca0132_use_alt_functions(spec))
8682 ca0132_alt_select_in(codec);
8683 else
8684 ca0132_select_mic(codec);
8685 }
8686
ca0132_setup_unsol(struct hda_codec * codec)8687 static void ca0132_setup_unsol(struct hda_codec *codec)
8688 {
8689 struct ca0132_spec *spec = codec->spec;
8690 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8691 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8692 amic_callback);
8693 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8694 ca0132_process_dsp_response);
8695 /* Front headphone jack detection */
8696 if (ca0132_use_alt_functions(spec))
8697 snd_hda_jack_detect_enable_callback(codec,
8698 spec->unsol_tag_front_hp, hp_callback);
8699 }
8700
8701 /*
8702 * Verbs tables.
8703 */
8704
8705 /* Sends before DSP download. */
8706 static const struct hda_verb ca0132_base_init_verbs[] = {
8707 /*enable ct extension*/
8708 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8709 {}
8710 };
8711
8712 /* Send at exit. */
8713 static const struct hda_verb ca0132_base_exit_verbs[] = {
8714 /*set afg to D3*/
8715 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8716 /*disable ct extension*/
8717 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8718 {}
8719 };
8720
8721 /* Other verbs tables. Sends after DSP download. */
8722
8723 static const struct hda_verb ca0132_init_verbs0[] = {
8724 /* chip init verbs */
8725 {0x15, 0x70D, 0xF0},
8726 {0x15, 0x70E, 0xFE},
8727 {0x15, 0x707, 0x75},
8728 {0x15, 0x707, 0xD3},
8729 {0x15, 0x707, 0x09},
8730 {0x15, 0x707, 0x53},
8731 {0x15, 0x707, 0xD4},
8732 {0x15, 0x707, 0xEF},
8733 {0x15, 0x707, 0x75},
8734 {0x15, 0x707, 0xD3},
8735 {0x15, 0x707, 0x09},
8736 {0x15, 0x707, 0x02},
8737 {0x15, 0x707, 0x37},
8738 {0x15, 0x707, 0x78},
8739 {0x15, 0x53C, 0xCE},
8740 {0x15, 0x575, 0xC9},
8741 {0x15, 0x53D, 0xCE},
8742 {0x15, 0x5B7, 0xC9},
8743 {0x15, 0x70D, 0xE8},
8744 {0x15, 0x70E, 0xFE},
8745 {0x15, 0x707, 0x02},
8746 {0x15, 0x707, 0x68},
8747 {0x15, 0x707, 0x62},
8748 {0x15, 0x53A, 0xCE},
8749 {0x15, 0x546, 0xC9},
8750 {0x15, 0x53B, 0xCE},
8751 {0x15, 0x5E8, 0xC9},
8752 {}
8753 };
8754
8755 /* Extra init verbs for desktop cards. */
8756 static const struct hda_verb ca0132_init_verbs1[] = {
8757 {0x15, 0x70D, 0x20},
8758 {0x15, 0x70E, 0x19},
8759 {0x15, 0x707, 0x00},
8760 {0x15, 0x539, 0xCE},
8761 {0x15, 0x546, 0xC9},
8762 {0x15, 0x70D, 0xB7},
8763 {0x15, 0x70E, 0x09},
8764 {0x15, 0x707, 0x10},
8765 {0x15, 0x70D, 0xAF},
8766 {0x15, 0x70E, 0x09},
8767 {0x15, 0x707, 0x01},
8768 {0x15, 0x707, 0x05},
8769 {0x15, 0x70D, 0x73},
8770 {0x15, 0x70E, 0x09},
8771 {0x15, 0x707, 0x14},
8772 {0x15, 0x6FF, 0xC4},
8773 {}
8774 };
8775
ca0132_init_chip(struct hda_codec * codec)8776 static void ca0132_init_chip(struct hda_codec *codec)
8777 {
8778 struct ca0132_spec *spec = codec->spec;
8779 int num_fx;
8780 int i;
8781 unsigned int on;
8782
8783 mutex_init(&spec->chipio_mutex);
8784
8785 /*
8786 * The Windows driver always does this upon startup, which seems to
8787 * clear out any previous configuration. This should help issues where
8788 * a boot into Windows prior to a boot into Linux breaks things. Also,
8789 * Windows always sends the reset twice.
8790 */
8791 if (ca0132_use_alt_functions(spec)) {
8792 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8793 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8794
8795 snd_hda_codec_write(codec, codec->core.afg, 0,
8796 AC_VERB_SET_CODEC_RESET, 0);
8797 snd_hda_codec_write(codec, codec->core.afg, 0,
8798 AC_VERB_SET_CODEC_RESET, 0);
8799 }
8800
8801 spec->cur_out_type = SPEAKER_OUT;
8802 if (!ca0132_use_alt_functions(spec))
8803 spec->cur_mic_type = DIGITAL_MIC;
8804 else
8805 spec->cur_mic_type = REAR_MIC;
8806
8807 spec->cur_mic_boost = 0;
8808
8809 for (i = 0; i < VNODES_COUNT; i++) {
8810 spec->vnode_lvol[i] = 0x5a;
8811 spec->vnode_rvol[i] = 0x5a;
8812 spec->vnode_lswitch[i] = 0;
8813 spec->vnode_rswitch[i] = 0;
8814 }
8815
8816 /*
8817 * Default states for effects are in ca0132_effects[].
8818 */
8819 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8820 for (i = 0; i < num_fx; i++) {
8821 on = (unsigned int)ca0132_effects[i].reqs[0];
8822 spec->effects_switch[i] = on ? 1 : 0;
8823 }
8824 /*
8825 * Sets defaults for the effect slider controls, only for alternative
8826 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8827 */
8828 if (ca0132_use_alt_controls(spec)) {
8829 /* Set speakers to default to full range. */
8830 spec->speaker_range_val[0] = 1;
8831 spec->speaker_range_val[1] = 1;
8832
8833 spec->xbass_xover_freq = 8;
8834 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8835 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8836
8837 spec->bass_redirect_xover_freq = 8;
8838 }
8839
8840 spec->voicefx_val = 0;
8841 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8842 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8843
8844 /*
8845 * The ZxR doesn't have a front panel header, and it's line-in is on
8846 * the daughter board. So, there is no input enum control, and we need
8847 * to make sure that spec->in_enum_val is set properly.
8848 */
8849 if (ca0132_quirk(spec) == QUIRK_ZXR)
8850 spec->in_enum_val = REAR_MIC;
8851
8852 #ifdef ENABLE_TUNING_CONTROLS
8853 ca0132_init_tuning_defaults(codec);
8854 #endif
8855 }
8856
8857 /*
8858 * Recon3Di exit specific commands.
8859 */
8860 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)8861 static void r3di_gpio_shutdown(struct hda_codec *codec)
8862 {
8863 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8864 }
8865
8866 /*
8867 * Sound Blaster Z exit specific commands.
8868 */
sbz_region2_exit(struct hda_codec * codec)8869 static void sbz_region2_exit(struct hda_codec *codec)
8870 {
8871 struct ca0132_spec *spec = codec->spec;
8872 unsigned int i;
8873
8874 for (i = 0; i < 4; i++)
8875 writeb(0x0, spec->mem_base + 0x100);
8876 for (i = 0; i < 8; i++)
8877 writeb(0xb3, spec->mem_base + 0x304);
8878
8879 ca0113_mmio_gpio_set(codec, 0, false);
8880 ca0113_mmio_gpio_set(codec, 1, false);
8881 ca0113_mmio_gpio_set(codec, 4, true);
8882 ca0113_mmio_gpio_set(codec, 5, false);
8883 ca0113_mmio_gpio_set(codec, 7, false);
8884 }
8885
sbz_set_pin_ctl_default(struct hda_codec * codec)8886 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8887 {
8888 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8889 unsigned int i;
8890
8891 snd_hda_codec_write(codec, 0x11, 0,
8892 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8893
8894 for (i = 0; i < ARRAY_SIZE(pins); i++)
8895 snd_hda_codec_write(codec, pins[i], 0,
8896 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8897 }
8898
ca0132_clear_unsolicited(struct hda_codec * codec)8899 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8900 {
8901 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8902 unsigned int i;
8903
8904 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8905 snd_hda_codec_write(codec, pins[i], 0,
8906 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8907 }
8908 }
8909
8910 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)8911 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8912 int mask, int data)
8913 {
8914 if (dir >= 0)
8915 snd_hda_codec_write(codec, 0x01, 0,
8916 AC_VERB_SET_GPIO_DIRECTION, dir);
8917 if (mask >= 0)
8918 snd_hda_codec_write(codec, 0x01, 0,
8919 AC_VERB_SET_GPIO_MASK, mask);
8920
8921 if (data >= 0)
8922 snd_hda_codec_write(codec, 0x01, 0,
8923 AC_VERB_SET_GPIO_DATA, data);
8924 }
8925
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)8926 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8927 {
8928 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8929 unsigned int i;
8930
8931 for (i = 0; i < ARRAY_SIZE(pins); i++)
8932 snd_hda_codec_write(codec, pins[i], 0,
8933 AC_VERB_SET_POWER_STATE, 0x03);
8934 }
8935
sbz_exit_chip(struct hda_codec * codec)8936 static void sbz_exit_chip(struct hda_codec *codec)
8937 {
8938 chipio_set_stream_control(codec, 0x03, 0);
8939 chipio_set_stream_control(codec, 0x04, 0);
8940
8941 /* Mess with GPIO */
8942 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8943 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8944 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8945
8946 chipio_set_stream_control(codec, 0x14, 0);
8947 chipio_set_stream_control(codec, 0x0C, 0);
8948
8949 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8950 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8951
8952 chipio_write(codec, 0x18a020, 0x00000083);
8953
8954 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8955 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8956 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8957
8958 chipio_set_stream_control(codec, 0x0C, 0);
8959
8960 chipio_set_control_param(codec, 0x0D, 0x24);
8961
8962 ca0132_clear_unsolicited(codec);
8963 sbz_set_pin_ctl_default(codec);
8964
8965 snd_hda_codec_write(codec, 0x0B, 0,
8966 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8967
8968 sbz_region2_exit(codec);
8969 }
8970
r3d_exit_chip(struct hda_codec * codec)8971 static void r3d_exit_chip(struct hda_codec *codec)
8972 {
8973 ca0132_clear_unsolicited(codec);
8974 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8975 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8976 }
8977
ae5_exit_chip(struct hda_codec * codec)8978 static void ae5_exit_chip(struct hda_codec *codec)
8979 {
8980 chipio_set_stream_control(codec, 0x03, 0);
8981 chipio_set_stream_control(codec, 0x04, 0);
8982
8983 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8984 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8985 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8986 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8987 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8988 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8989 ca0113_mmio_gpio_set(codec, 0, false);
8990 ca0113_mmio_gpio_set(codec, 1, false);
8991
8992 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8993 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8994
8995 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8996
8997 chipio_set_stream_control(codec, 0x18, 0);
8998 chipio_set_stream_control(codec, 0x0c, 0);
8999
9000 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
9001 }
9002
ae7_exit_chip(struct hda_codec * codec)9003 static void ae7_exit_chip(struct hda_codec *codec)
9004 {
9005 chipio_set_stream_control(codec, 0x18, 0);
9006 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9007 chipio_set_stream_channels(codec, 0x21, 0);
9008 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9009 chipio_set_control_param(codec, 0x20, 0x01);
9010
9011 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9012
9013 chipio_set_stream_control(codec, 0x18, 0);
9014 chipio_set_stream_control(codec, 0x0c, 0);
9015
9016 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9017 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9018 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9019 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9020 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9021 ca0113_mmio_gpio_set(codec, 0, false);
9022 ca0113_mmio_gpio_set(codec, 1, false);
9023 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9024
9025 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9026 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9027 }
9028
zxr_exit_chip(struct hda_codec * codec)9029 static void zxr_exit_chip(struct hda_codec *codec)
9030 {
9031 chipio_set_stream_control(codec, 0x03, 0);
9032 chipio_set_stream_control(codec, 0x04, 0);
9033 chipio_set_stream_control(codec, 0x14, 0);
9034 chipio_set_stream_control(codec, 0x0C, 0);
9035
9036 chipio_set_conn_rate(codec, 0x41, SR_192_000);
9037 chipio_set_conn_rate(codec, 0x91, SR_192_000);
9038
9039 chipio_write(codec, 0x18a020, 0x00000083);
9040
9041 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9042 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9043
9044 ca0132_clear_unsolicited(codec);
9045 sbz_set_pin_ctl_default(codec);
9046 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9047
9048 ca0113_mmio_gpio_set(codec, 5, false);
9049 ca0113_mmio_gpio_set(codec, 2, false);
9050 ca0113_mmio_gpio_set(codec, 3, false);
9051 ca0113_mmio_gpio_set(codec, 0, false);
9052 ca0113_mmio_gpio_set(codec, 4, true);
9053 ca0113_mmio_gpio_set(codec, 0, true);
9054 ca0113_mmio_gpio_set(codec, 5, true);
9055 ca0113_mmio_gpio_set(codec, 2, false);
9056 ca0113_mmio_gpio_set(codec, 3, false);
9057 }
9058
ca0132_exit_chip(struct hda_codec * codec)9059 static void ca0132_exit_chip(struct hda_codec *codec)
9060 {
9061 /* put any chip cleanup stuffs here. */
9062
9063 if (dspload_is_loaded(codec))
9064 dsp_reset(codec);
9065 }
9066
9067 /*
9068 * This fixes a problem that was hard to reproduce. Very rarely, I would
9069 * boot up, and there would be no sound, but the DSP indicated it had loaded
9070 * properly. I did a few memory dumps to see if anything was different, and
9071 * there were a few areas of memory uninitialized with a1a2a3a4. This function
9072 * checks if those areas are uninitialized, and if they are, it'll attempt to
9073 * reload the card 3 times. Usually it fixes by the second.
9074 */
sbz_dsp_startup_check(struct hda_codec * codec)9075 static void sbz_dsp_startup_check(struct hda_codec *codec)
9076 {
9077 struct ca0132_spec *spec = codec->spec;
9078 unsigned int dsp_data_check[4];
9079 unsigned int cur_address = 0x390;
9080 unsigned int i;
9081 unsigned int failure = 0;
9082 unsigned int reload = 3;
9083
9084 if (spec->startup_check_entered)
9085 return;
9086
9087 spec->startup_check_entered = true;
9088
9089 for (i = 0; i < 4; i++) {
9090 chipio_read(codec, cur_address, &dsp_data_check[i]);
9091 cur_address += 0x4;
9092 }
9093 for (i = 0; i < 4; i++) {
9094 if (dsp_data_check[i] == 0xa1a2a3a4)
9095 failure = 1;
9096 }
9097
9098 codec_dbg(codec, "Startup Check: %d ", failure);
9099 if (failure)
9100 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9101 /*
9102 * While the failure condition is true, and we haven't reached our
9103 * three reload limit, continue trying to reload the driver and
9104 * fix the issue.
9105 */
9106 while (failure && (reload != 0)) {
9107 codec_info(codec, "Reloading... Tries left: %d", reload);
9108 sbz_exit_chip(codec);
9109 spec->dsp_state = DSP_DOWNLOAD_INIT;
9110 codec->patch_ops.init(codec);
9111 failure = 0;
9112 for (i = 0; i < 4; i++) {
9113 chipio_read(codec, cur_address, &dsp_data_check[i]);
9114 cur_address += 0x4;
9115 }
9116 for (i = 0; i < 4; i++) {
9117 if (dsp_data_check[i] == 0xa1a2a3a4)
9118 failure = 1;
9119 }
9120 reload--;
9121 }
9122
9123 if (!failure && reload < 3)
9124 codec_info(codec, "DSP fixed.");
9125
9126 if (!failure)
9127 return;
9128
9129 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9130 }
9131
9132 /*
9133 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9134 * extra precision for decibel values. If you had the dB value in floating point
9135 * you would take the value after the decimal point, multiply by 64, and divide
9136 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9137 * implement fixed point or floating point dB volumes. For now, I'll set them
9138 * to 0 just incase a value has lingered from a boot into Windows.
9139 */
ca0132_alt_vol_setup(struct hda_codec * codec)9140 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9141 {
9142 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9143 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9144 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9145 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9146 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9147 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9148 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9149 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9150 }
9151
9152 /*
9153 * Extra commands that don't really fit anywhere else.
9154 */
sbz_pre_dsp_setup(struct hda_codec * codec)9155 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9156 {
9157 struct ca0132_spec *spec = codec->spec;
9158
9159 writel(0x00820680, spec->mem_base + 0x01C);
9160 writel(0x00820680, spec->mem_base + 0x01C);
9161
9162 chipio_write(codec, 0x18b0a4, 0x000000c2);
9163
9164 snd_hda_codec_write(codec, 0x11, 0,
9165 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9166 }
9167
r3d_pre_dsp_setup(struct hda_codec * codec)9168 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9169 {
9170 chipio_write(codec, 0x18b0a4, 0x000000c2);
9171
9172 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9173
9174 snd_hda_codec_write(codec, 0x11, 0,
9175 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9176 }
9177
r3di_pre_dsp_setup(struct hda_codec * codec)9178 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9179 {
9180 chipio_write(codec, 0x18b0a4, 0x000000c2);
9181
9182 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9183 chipio_8051_write_exram(codec, 0x1920, 0x00);
9184 chipio_8051_write_exram(codec, 0x1921, 0x40);
9185
9186 snd_hda_codec_write(codec, 0x11, 0,
9187 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9188 }
9189
9190 /*
9191 * The ZxR seems to use alternative DAC's for the surround channels, which
9192 * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9193 * this up, we get no audio out of the surround jacks.
9194 */
zxr_pre_dsp_setup(struct hda_codec * codec)9195 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9196 {
9197 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9198 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9199 unsigned int i;
9200
9201 chipio_write(codec, 0x189000, 0x0001f100);
9202 msleep(50);
9203 chipio_write(codec, 0x18900c, 0x0001f100);
9204 msleep(50);
9205
9206 /*
9207 * This writes a RET instruction at the entry point of the function at
9208 * 0xfa92 in exram. This function seems to have something to do with
9209 * ASI. Might be some way to prevent the card from reconfiguring the
9210 * ASI stuff itself.
9211 */
9212 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9213
9214 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9215
9216 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9217 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9218
9219 chipio_write(codec, 0x18902c, 0x00000000);
9220 msleep(50);
9221 chipio_write(codec, 0x18902c, 0x00000003);
9222 msleep(50);
9223
9224 for (i = 0; i < ARRAY_SIZE(addr); i++)
9225 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9226 }
9227
9228 /*
9229 * These are sent before the DSP is downloaded. Not sure
9230 * what they do, or if they're necessary. Could possibly
9231 * be removed. Figure they're better to leave in.
9232 */
9233 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9234 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9235 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9236 };
9237
9238 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9239 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9240 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9241 0x000000c1, 0x00000080
9242 };
9243
9244 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9245 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9246 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9247 0x000000c1, 0x00000080
9248 };
9249
9250 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9251 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9252 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9253 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9254 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9255 };
9256
9257 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9258 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9259 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9260 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9261 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9262 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9263 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9264 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9265 0x00000080, 0x00880680
9266 };
9267
ca0132_mmio_init_sbz(struct hda_codec * codec)9268 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9269 {
9270 struct ca0132_spec *spec = codec->spec;
9271 unsigned int tmp[2], i, count, cur_addr;
9272 const unsigned int *addr, *data;
9273
9274 addr = ca0113_mmio_init_address_sbz;
9275 for (i = 0; i < 3; i++)
9276 writel(0x00000000, spec->mem_base + addr[i]);
9277
9278 cur_addr = i;
9279 switch (ca0132_quirk(spec)) {
9280 case QUIRK_ZXR:
9281 tmp[0] = 0x00880480;
9282 tmp[1] = 0x00000080;
9283 break;
9284 case QUIRK_SBZ:
9285 tmp[0] = 0x00820680;
9286 tmp[1] = 0x00000083;
9287 break;
9288 case QUIRK_R3D:
9289 tmp[0] = 0x00880680;
9290 tmp[1] = 0x00000083;
9291 break;
9292 default:
9293 tmp[0] = 0x00000000;
9294 tmp[1] = 0x00000000;
9295 break;
9296 }
9297
9298 for (i = 0; i < 2; i++)
9299 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9300
9301 cur_addr += i;
9302
9303 switch (ca0132_quirk(spec)) {
9304 case QUIRK_ZXR:
9305 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9306 data = ca0113_mmio_init_data_zxr;
9307 break;
9308 default:
9309 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9310 data = ca0113_mmio_init_data_sbz;
9311 break;
9312 }
9313
9314 for (i = 0; i < count; i++)
9315 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9316 }
9317
ca0132_mmio_init_ae5(struct hda_codec * codec)9318 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9319 {
9320 struct ca0132_spec *spec = codec->spec;
9321 const unsigned int *addr, *data;
9322 unsigned int i, count;
9323
9324 addr = ca0113_mmio_init_address_ae5;
9325 data = ca0113_mmio_init_data_ae5;
9326 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9327
9328 if (ca0132_quirk(spec) == QUIRK_AE7) {
9329 writel(0x00000680, spec->mem_base + 0x1c);
9330 writel(0x00880680, spec->mem_base + 0x1c);
9331 }
9332
9333 for (i = 0; i < count; i++) {
9334 /*
9335 * AE-7 shares all writes with the AE-5, except that it writes
9336 * a different value to 0x20c.
9337 */
9338 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9339 writel(0x00800001, spec->mem_base + addr[i]);
9340 continue;
9341 }
9342
9343 writel(data[i], spec->mem_base + addr[i]);
9344 }
9345
9346 if (ca0132_quirk(spec) == QUIRK_AE5)
9347 writel(0x00880680, spec->mem_base + 0x1c);
9348 }
9349
ca0132_mmio_init(struct hda_codec * codec)9350 static void ca0132_mmio_init(struct hda_codec *codec)
9351 {
9352 struct ca0132_spec *spec = codec->spec;
9353
9354 switch (ca0132_quirk(spec)) {
9355 case QUIRK_R3D:
9356 case QUIRK_SBZ:
9357 case QUIRK_ZXR:
9358 ca0132_mmio_init_sbz(codec);
9359 break;
9360 case QUIRK_AE5:
9361 ca0132_mmio_init_ae5(codec);
9362 break;
9363 default:
9364 break;
9365 }
9366 }
9367
9368 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9369 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9370 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9371 };
9372
9373 static const unsigned char ca0132_ae5_register_set_data[] = {
9374 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9375 0x01, 0x6b, 0x57
9376 };
9377
9378 /*
9379 * This function writes to some SFR's, does some region2 writes, and then
9380 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9381 * what it does.
9382 */
ae5_register_set(struct hda_codec * codec)9383 static void ae5_register_set(struct hda_codec *codec)
9384 {
9385 struct ca0132_spec *spec = codec->spec;
9386 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9387 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9388 const unsigned char *data = ca0132_ae5_register_set_data;
9389 unsigned int i, cur_addr;
9390 unsigned char tmp[3];
9391
9392 if (ca0132_quirk(spec) == QUIRK_AE7)
9393 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9394
9395 chipio_8051_write_direct(codec, 0x93, 0x10);
9396 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9397
9398 if (ca0132_quirk(spec) == QUIRK_AE7) {
9399 tmp[0] = 0x03;
9400 tmp[1] = 0x03;
9401 tmp[2] = 0x07;
9402 } else {
9403 tmp[0] = 0x0f;
9404 tmp[1] = 0x0f;
9405 tmp[2] = 0x0f;
9406 }
9407
9408 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9409 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9410
9411 /*
9412 * First writes are in single bytes, final are in 4 bytes. So, we use
9413 * writeb, then writel.
9414 */
9415 for (i = 0; cur_addr < 12; i++, cur_addr++)
9416 writeb(data[i], spec->mem_base + addr[cur_addr]);
9417
9418 for (; cur_addr < count; i++, cur_addr++)
9419 writel(data[i], spec->mem_base + addr[cur_addr]);
9420
9421 writel(0x00800001, spec->mem_base + 0x20c);
9422
9423 if (ca0132_quirk(spec) == QUIRK_AE7) {
9424 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9425 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9426 } else {
9427 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9428 }
9429
9430 chipio_8051_write_direct(codec, 0x90, 0x00);
9431 chipio_8051_write_direct(codec, 0x90, 0x10);
9432
9433 if (ca0132_quirk(spec) == QUIRK_AE5)
9434 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9435 }
9436
9437 /*
9438 * Extra init functions for alternative ca0132 codecs. Done
9439 * here so they don't clutter up the main ca0132_init function
9440 * anymore than they have to.
9441 */
ca0132_alt_init(struct hda_codec * codec)9442 static void ca0132_alt_init(struct hda_codec *codec)
9443 {
9444 struct ca0132_spec *spec = codec->spec;
9445
9446 ca0132_alt_vol_setup(codec);
9447
9448 switch (ca0132_quirk(spec)) {
9449 case QUIRK_SBZ:
9450 codec_dbg(codec, "SBZ alt_init");
9451 ca0132_gpio_init(codec);
9452 sbz_pre_dsp_setup(codec);
9453 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9454 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9455 break;
9456 case QUIRK_R3DI:
9457 codec_dbg(codec, "R3DI alt_init");
9458 ca0132_gpio_init(codec);
9459 ca0132_gpio_setup(codec);
9460 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9461 r3di_pre_dsp_setup(codec);
9462 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9463 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9464 break;
9465 case QUIRK_R3D:
9466 r3d_pre_dsp_setup(codec);
9467 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9468 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9469 break;
9470 case QUIRK_AE5:
9471 ca0132_gpio_init(codec);
9472 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9473 chipio_write(codec, 0x18b030, 0x00000020);
9474 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9475 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9476 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9477 break;
9478 case QUIRK_AE7:
9479 ca0132_gpio_init(codec);
9480 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9481 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9482 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9483 chipio_write(codec, 0x18b008, 0x000000f8);
9484 chipio_write(codec, 0x18b008, 0x000000f0);
9485 chipio_write(codec, 0x18b030, 0x00000020);
9486 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9487 break;
9488 case QUIRK_ZXR:
9489 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9490 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9491 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9492 zxr_pre_dsp_setup(codec);
9493 break;
9494 default:
9495 break;
9496 }
9497 }
9498
ca0132_init(struct hda_codec * codec)9499 static int ca0132_init(struct hda_codec *codec)
9500 {
9501 struct ca0132_spec *spec = codec->spec;
9502 struct auto_pin_cfg *cfg = &spec->autocfg;
9503 int i;
9504 bool dsp_loaded;
9505
9506 /*
9507 * If the DSP is already downloaded, and init has been entered again,
9508 * there's only two reasons for it. One, the codec has awaken from a
9509 * suspended state, and in that case dspload_is_loaded will return
9510 * false, and the init will be ran again. The other reason it gets
9511 * re entered is on startup for some reason it triggers a suspend and
9512 * resume state. In this case, it will check if the DSP is downloaded,
9513 * and not run the init function again. For codecs using alt_functions,
9514 * it will check if the DSP is loaded properly.
9515 */
9516 if (spec->dsp_state == DSP_DOWNLOADED) {
9517 dsp_loaded = dspload_is_loaded(codec);
9518 if (!dsp_loaded) {
9519 spec->dsp_reload = true;
9520 spec->dsp_state = DSP_DOWNLOAD_INIT;
9521 } else {
9522 if (ca0132_quirk(spec) == QUIRK_SBZ)
9523 sbz_dsp_startup_check(codec);
9524 return 0;
9525 }
9526 }
9527
9528 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9529 spec->dsp_state = DSP_DOWNLOAD_INIT;
9530 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9531
9532 if (ca0132_use_pci_mmio(spec))
9533 ca0132_mmio_init(codec);
9534
9535 snd_hda_power_up_pm(codec);
9536
9537 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9538 ae5_register_set(codec);
9539
9540 ca0132_init_params(codec);
9541 ca0132_init_flags(codec);
9542
9543 snd_hda_sequence_write(codec, spec->base_init_verbs);
9544
9545 if (ca0132_use_alt_functions(spec))
9546 ca0132_alt_init(codec);
9547
9548 ca0132_download_dsp(codec);
9549
9550 ca0132_refresh_widget_caps(codec);
9551
9552 switch (ca0132_quirk(spec)) {
9553 case QUIRK_R3DI:
9554 case QUIRK_R3D:
9555 r3d_setup_defaults(codec);
9556 break;
9557 case QUIRK_SBZ:
9558 case QUIRK_ZXR:
9559 sbz_setup_defaults(codec);
9560 break;
9561 case QUIRK_AE5:
9562 ae5_setup_defaults(codec);
9563 break;
9564 case QUIRK_AE7:
9565 ae7_setup_defaults(codec);
9566 break;
9567 default:
9568 ca0132_setup_defaults(codec);
9569 ca0132_init_analog_mic2(codec);
9570 ca0132_init_dmic(codec);
9571 break;
9572 }
9573
9574 for (i = 0; i < spec->num_outputs; i++)
9575 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9576
9577 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9578
9579 for (i = 0; i < spec->num_inputs; i++)
9580 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9581
9582 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9583
9584 if (!ca0132_use_alt_functions(spec)) {
9585 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9586 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9587 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9588 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9589 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9590 }
9591
9592 if (ca0132_quirk(spec) == QUIRK_SBZ)
9593 ca0132_gpio_setup(codec);
9594
9595 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9596 if (ca0132_use_alt_functions(spec)) {
9597 ca0132_alt_select_out(codec);
9598 ca0132_alt_select_in(codec);
9599 } else {
9600 ca0132_select_out(codec);
9601 ca0132_select_mic(codec);
9602 }
9603
9604 snd_hda_jack_report_sync(codec);
9605
9606 /*
9607 * Re set the PlayEnhancement switch on a resume event, because the
9608 * controls will not be reloaded.
9609 */
9610 if (spec->dsp_reload) {
9611 spec->dsp_reload = false;
9612 ca0132_pe_switch_set(codec);
9613 }
9614
9615 snd_hda_power_down_pm(codec);
9616
9617 return 0;
9618 }
9619
dbpro_init(struct hda_codec * codec)9620 static int dbpro_init(struct hda_codec *codec)
9621 {
9622 struct ca0132_spec *spec = codec->spec;
9623 struct auto_pin_cfg *cfg = &spec->autocfg;
9624 unsigned int i;
9625
9626 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9627 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9628
9629 for (i = 0; i < spec->num_inputs; i++)
9630 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9631
9632 return 0;
9633 }
9634
ca0132_free(struct hda_codec * codec)9635 static void ca0132_free(struct hda_codec *codec)
9636 {
9637 struct ca0132_spec *spec = codec->spec;
9638
9639 cancel_delayed_work_sync(&spec->unsol_hp_work);
9640 snd_hda_power_up(codec);
9641 switch (ca0132_quirk(spec)) {
9642 case QUIRK_SBZ:
9643 sbz_exit_chip(codec);
9644 break;
9645 case QUIRK_ZXR:
9646 zxr_exit_chip(codec);
9647 break;
9648 case QUIRK_R3D:
9649 r3d_exit_chip(codec);
9650 break;
9651 case QUIRK_AE5:
9652 ae5_exit_chip(codec);
9653 break;
9654 case QUIRK_AE7:
9655 ae7_exit_chip(codec);
9656 break;
9657 case QUIRK_R3DI:
9658 r3di_gpio_shutdown(codec);
9659 break;
9660 default:
9661 break;
9662 }
9663
9664 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9665 ca0132_exit_chip(codec);
9666
9667 snd_hda_power_down(codec);
9668 #ifdef CONFIG_PCI
9669 if (spec->mem_base)
9670 pci_iounmap(codec->bus->pci, spec->mem_base);
9671 #endif
9672 kfree(spec->spec_init_verbs);
9673 kfree(codec->spec);
9674 }
9675
dbpro_free(struct hda_codec * codec)9676 static void dbpro_free(struct hda_codec *codec)
9677 {
9678 struct ca0132_spec *spec = codec->spec;
9679
9680 zxr_dbpro_power_state_shutdown(codec);
9681
9682 kfree(spec->spec_init_verbs);
9683 kfree(codec->spec);
9684 }
9685
9686 #ifdef CONFIG_PM
ca0132_suspend(struct hda_codec * codec)9687 static int ca0132_suspend(struct hda_codec *codec)
9688 {
9689 struct ca0132_spec *spec = codec->spec;
9690
9691 cancel_delayed_work_sync(&spec->unsol_hp_work);
9692 return 0;
9693 }
9694 #endif
9695
9696 static const struct hda_codec_ops ca0132_patch_ops = {
9697 .build_controls = ca0132_build_controls,
9698 .build_pcms = ca0132_build_pcms,
9699 .init = ca0132_init,
9700 .free = ca0132_free,
9701 .unsol_event = snd_hda_jack_unsol_event,
9702 #ifdef CONFIG_PM
9703 .suspend = ca0132_suspend,
9704 #endif
9705 };
9706
9707 static const struct hda_codec_ops dbpro_patch_ops = {
9708 .build_controls = dbpro_build_controls,
9709 .build_pcms = dbpro_build_pcms,
9710 .init = dbpro_init,
9711 .free = dbpro_free,
9712 };
9713
ca0132_config(struct hda_codec * codec)9714 static void ca0132_config(struct hda_codec *codec)
9715 {
9716 struct ca0132_spec *spec = codec->spec;
9717
9718 spec->dacs[0] = 0x2;
9719 spec->dacs[1] = 0x3;
9720 spec->dacs[2] = 0x4;
9721
9722 spec->multiout.dac_nids = spec->dacs;
9723 spec->multiout.num_dacs = 3;
9724
9725 if (!ca0132_use_alt_functions(spec))
9726 spec->multiout.max_channels = 2;
9727 else
9728 spec->multiout.max_channels = 6;
9729
9730 switch (ca0132_quirk(spec)) {
9731 case QUIRK_ALIENWARE:
9732 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9733 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9734 break;
9735 case QUIRK_SBZ:
9736 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9737 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9738 break;
9739 case QUIRK_ZXR:
9740 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9741 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9742 break;
9743 case QUIRK_R3D:
9744 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9745 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9746 break;
9747 case QUIRK_R3DI:
9748 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9749 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9750 break;
9751 case QUIRK_AE5:
9752 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9753 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9754 break;
9755 case QUIRK_AE7:
9756 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9757 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9758 break;
9759 default:
9760 break;
9761 }
9762
9763 switch (ca0132_quirk(spec)) {
9764 case QUIRK_ALIENWARE:
9765 spec->num_outputs = 2;
9766 spec->out_pins[0] = 0x0b; /* speaker out */
9767 spec->out_pins[1] = 0x0f;
9768 spec->shared_out_nid = 0x2;
9769 spec->unsol_tag_hp = 0x0f;
9770
9771 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9772 spec->adcs[1] = 0x8; /* analog mic2 */
9773 spec->adcs[2] = 0xa; /* what u hear */
9774
9775 spec->num_inputs = 3;
9776 spec->input_pins[0] = 0x12;
9777 spec->input_pins[1] = 0x11;
9778 spec->input_pins[2] = 0x13;
9779 spec->shared_mic_nid = 0x7;
9780 spec->unsol_tag_amic1 = 0x11;
9781 break;
9782 case QUIRK_SBZ:
9783 case QUIRK_R3D:
9784 spec->num_outputs = 2;
9785 spec->out_pins[0] = 0x0B; /* Line out */
9786 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9787 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9788 spec->out_pins[3] = 0x11; /* Rear surround */
9789 spec->shared_out_nid = 0x2;
9790 spec->unsol_tag_hp = spec->out_pins[1];
9791 spec->unsol_tag_front_hp = spec->out_pins[2];
9792
9793 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9794 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9795 spec->adcs[2] = 0xa; /* what u hear */
9796
9797 spec->num_inputs = 2;
9798 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9799 spec->input_pins[1] = 0x13; /* What U Hear */
9800 spec->shared_mic_nid = 0x7;
9801 spec->unsol_tag_amic1 = spec->input_pins[0];
9802
9803 /* SPDIF I/O */
9804 spec->dig_out = 0x05;
9805 spec->multiout.dig_out_nid = spec->dig_out;
9806 spec->dig_in = 0x09;
9807 break;
9808 case QUIRK_ZXR:
9809 spec->num_outputs = 2;
9810 spec->out_pins[0] = 0x0B; /* Line out */
9811 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9812 spec->out_pins[2] = 0x10; /* Center/LFE */
9813 spec->out_pins[3] = 0x11; /* Rear surround */
9814 spec->shared_out_nid = 0x2;
9815 spec->unsol_tag_hp = spec->out_pins[1];
9816 spec->unsol_tag_front_hp = spec->out_pins[2];
9817
9818 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9819 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9820 spec->adcs[2] = 0xa; /* what u hear */
9821
9822 spec->num_inputs = 2;
9823 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9824 spec->input_pins[1] = 0x13; /* What U Hear */
9825 spec->shared_mic_nid = 0x7;
9826 spec->unsol_tag_amic1 = spec->input_pins[0];
9827 break;
9828 case QUIRK_ZXR_DBPRO:
9829 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9830
9831 spec->num_inputs = 1;
9832 spec->input_pins[0] = 0x11; /* RCA Line-in */
9833
9834 spec->dig_out = 0x05;
9835 spec->multiout.dig_out_nid = spec->dig_out;
9836
9837 spec->dig_in = 0x09;
9838 break;
9839 case QUIRK_AE5:
9840 case QUIRK_AE7:
9841 spec->num_outputs = 2;
9842 spec->out_pins[0] = 0x0B; /* Line out */
9843 spec->out_pins[1] = 0x11; /* Rear headphone out */
9844 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9845 spec->out_pins[3] = 0x0F; /* Rear surround */
9846 spec->shared_out_nid = 0x2;
9847 spec->unsol_tag_hp = spec->out_pins[1];
9848 spec->unsol_tag_front_hp = spec->out_pins[2];
9849
9850 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9851 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9852 spec->adcs[2] = 0xa; /* what u hear */
9853
9854 spec->num_inputs = 2;
9855 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9856 spec->input_pins[1] = 0x13; /* What U Hear */
9857 spec->shared_mic_nid = 0x7;
9858 spec->unsol_tag_amic1 = spec->input_pins[0];
9859
9860 /* SPDIF I/O */
9861 spec->dig_out = 0x05;
9862 spec->multiout.dig_out_nid = spec->dig_out;
9863 break;
9864 case QUIRK_R3DI:
9865 spec->num_outputs = 2;
9866 spec->out_pins[0] = 0x0B; /* Line out */
9867 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9868 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9869 spec->out_pins[3] = 0x11; /* Rear surround */
9870 spec->shared_out_nid = 0x2;
9871 spec->unsol_tag_hp = spec->out_pins[1];
9872 spec->unsol_tag_front_hp = spec->out_pins[2];
9873
9874 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9875 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9876 spec->adcs[2] = 0x0a; /* what u hear */
9877
9878 spec->num_inputs = 2;
9879 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9880 spec->input_pins[1] = 0x13; /* What U Hear */
9881 spec->shared_mic_nid = 0x7;
9882 spec->unsol_tag_amic1 = spec->input_pins[0];
9883
9884 /* SPDIF I/O */
9885 spec->dig_out = 0x05;
9886 spec->multiout.dig_out_nid = spec->dig_out;
9887 break;
9888 default:
9889 spec->num_outputs = 2;
9890 spec->out_pins[0] = 0x0b; /* speaker out */
9891 spec->out_pins[1] = 0x10; /* headphone out */
9892 spec->shared_out_nid = 0x2;
9893 spec->unsol_tag_hp = spec->out_pins[1];
9894
9895 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9896 spec->adcs[1] = 0x8; /* analog mic2 */
9897 spec->adcs[2] = 0xa; /* what u hear */
9898
9899 spec->num_inputs = 3;
9900 spec->input_pins[0] = 0x12;
9901 spec->input_pins[1] = 0x11;
9902 spec->input_pins[2] = 0x13;
9903 spec->shared_mic_nid = 0x7;
9904 spec->unsol_tag_amic1 = spec->input_pins[0];
9905
9906 /* SPDIF I/O */
9907 spec->dig_out = 0x05;
9908 spec->multiout.dig_out_nid = spec->dig_out;
9909 spec->dig_in = 0x09;
9910 break;
9911 }
9912 }
9913
ca0132_prepare_verbs(struct hda_codec * codec)9914 static int ca0132_prepare_verbs(struct hda_codec *codec)
9915 {
9916 /* Verbs + terminator (an empty element) */
9917 #define NUM_SPEC_VERBS 2
9918 struct ca0132_spec *spec = codec->spec;
9919
9920 spec->chip_init_verbs = ca0132_init_verbs0;
9921 /*
9922 * Since desktop cards use pci_mmio, this can be used to determine
9923 * whether or not to use these verbs instead of a separate bool.
9924 */
9925 if (ca0132_use_pci_mmio(spec))
9926 spec->desktop_init_verbs = ca0132_init_verbs1;
9927 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9928 sizeof(struct hda_verb),
9929 GFP_KERNEL);
9930 if (!spec->spec_init_verbs)
9931 return -ENOMEM;
9932
9933 /* config EAPD */
9934 spec->spec_init_verbs[0].nid = 0x0b;
9935 spec->spec_init_verbs[0].param = 0x78D;
9936 spec->spec_init_verbs[0].verb = 0x00;
9937
9938 /* Previously commented configuration */
9939 /*
9940 spec->spec_init_verbs[2].nid = 0x0b;
9941 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9942 spec->spec_init_verbs[2].verb = 0x02;
9943
9944 spec->spec_init_verbs[3].nid = 0x10;
9945 spec->spec_init_verbs[3].param = 0x78D;
9946 spec->spec_init_verbs[3].verb = 0x02;
9947
9948 spec->spec_init_verbs[4].nid = 0x10;
9949 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9950 spec->spec_init_verbs[4].verb = 0x02;
9951 */
9952
9953 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9954 return 0;
9955 }
9956
9957 /*
9958 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9959 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9960 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9961 * daughter boards ID.
9962 */
sbz_detect_quirk(struct hda_codec * codec)9963 static void sbz_detect_quirk(struct hda_codec *codec)
9964 {
9965 struct ca0132_spec *spec = codec->spec;
9966
9967 switch (codec->core.subsystem_id) {
9968 case 0x11020033:
9969 spec->quirk = QUIRK_ZXR;
9970 break;
9971 case 0x1102003f:
9972 spec->quirk = QUIRK_ZXR_DBPRO;
9973 break;
9974 default:
9975 spec->quirk = QUIRK_SBZ;
9976 break;
9977 }
9978 }
9979
patch_ca0132(struct hda_codec * codec)9980 static int patch_ca0132(struct hda_codec *codec)
9981 {
9982 struct ca0132_spec *spec;
9983 int err;
9984 const struct snd_pci_quirk *quirk;
9985
9986 codec_dbg(codec, "patch_ca0132\n");
9987
9988 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9989 if (!spec)
9990 return -ENOMEM;
9991 codec->spec = spec;
9992 spec->codec = codec;
9993
9994 /* Detect codec quirk */
9995 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9996 if (quirk)
9997 spec->quirk = quirk->value;
9998 else
9999 spec->quirk = QUIRK_NONE;
10000 if (ca0132_quirk(spec) == QUIRK_SBZ)
10001 sbz_detect_quirk(codec);
10002
10003 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10004 codec->patch_ops = dbpro_patch_ops;
10005 else
10006 codec->patch_ops = ca0132_patch_ops;
10007
10008 codec->pcm_format_first = 1;
10009 codec->no_sticky_stream = 1;
10010
10011
10012 spec->dsp_state = DSP_DOWNLOAD_INIT;
10013 spec->num_mixers = 1;
10014
10015 /* Set which mixers each quirk uses. */
10016 switch (ca0132_quirk(spec)) {
10017 case QUIRK_SBZ:
10018 spec->mixers[0] = desktop_mixer;
10019 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10020 break;
10021 case QUIRK_ZXR:
10022 spec->mixers[0] = desktop_mixer;
10023 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10024 break;
10025 case QUIRK_ZXR_DBPRO:
10026 break;
10027 case QUIRK_R3D:
10028 spec->mixers[0] = desktop_mixer;
10029 snd_hda_codec_set_name(codec, "Recon3D");
10030 break;
10031 case QUIRK_R3DI:
10032 spec->mixers[0] = r3di_mixer;
10033 snd_hda_codec_set_name(codec, "Recon3Di");
10034 break;
10035 case QUIRK_AE5:
10036 spec->mixers[0] = desktop_mixer;
10037 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10038 break;
10039 case QUIRK_AE7:
10040 spec->mixers[0] = desktop_mixer;
10041 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10042 break;
10043 default:
10044 spec->mixers[0] = ca0132_mixer;
10045 break;
10046 }
10047
10048 /* Setup whether or not to use alt functions/controls/pci_mmio */
10049 switch (ca0132_quirk(spec)) {
10050 case QUIRK_SBZ:
10051 case QUIRK_R3D:
10052 case QUIRK_AE5:
10053 case QUIRK_AE7:
10054 case QUIRK_ZXR:
10055 spec->use_alt_controls = true;
10056 spec->use_alt_functions = true;
10057 spec->use_pci_mmio = true;
10058 break;
10059 case QUIRK_R3DI:
10060 spec->use_alt_controls = true;
10061 spec->use_alt_functions = true;
10062 spec->use_pci_mmio = false;
10063 break;
10064 default:
10065 spec->use_alt_controls = false;
10066 spec->use_alt_functions = false;
10067 spec->use_pci_mmio = false;
10068 break;
10069 }
10070
10071 #ifdef CONFIG_PCI
10072 if (spec->use_pci_mmio) {
10073 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10074 if (spec->mem_base == NULL) {
10075 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10076 spec->quirk = QUIRK_NONE;
10077 }
10078 }
10079 #endif
10080
10081 spec->base_init_verbs = ca0132_base_init_verbs;
10082 spec->base_exit_verbs = ca0132_base_exit_verbs;
10083
10084 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10085
10086 ca0132_init_chip(codec);
10087
10088 ca0132_config(codec);
10089
10090 err = ca0132_prepare_verbs(codec);
10091 if (err < 0)
10092 goto error;
10093
10094 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10095 if (err < 0)
10096 goto error;
10097
10098 ca0132_setup_unsol(codec);
10099
10100 return 0;
10101
10102 error:
10103 ca0132_free(codec);
10104 return err;
10105 }
10106
10107 /*
10108 * patch entries
10109 */
10110 static const struct hda_device_id snd_hda_id_ca0132[] = {
10111 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
10112 {} /* terminator */
10113 };
10114 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10115
10116 MODULE_LICENSE("GPL");
10117 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10118
10119 static struct hda_codec_driver ca0132_driver = {
10120 .id = snd_hda_id_ca0132,
10121 };
10122
10123 module_hda_codec_driver(ca0132_driver);
10124