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Searched refs:CLK_WDT (Results 1 – 18 of 18) sorted by relevance

/linux-6.6.21/include/dt-bindings/clock/
Dexynos5410.h51 #define CLK_WDT 316 macro
Dexynos5250.h140 #define CLK_WDT 336 macro
Ds5pv210.h156 #define CLK_WDT 138 macro
Dexynos5420.h109 #define CLK_WDT 316 macro
Dexynos4.h183 #define CLK_WDT 345 macro
Dexynos3250.h152 #define CLK_WDT 146 macro
/linux-6.6.21/drivers/clk/samsung/
Dclk-exynos5410.c171 GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
Dclk-s5pv210.c572 GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
Dclk-exynos4.c951 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
1002 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
Dclk-exynos5250.c629 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
Dclk-exynos3250.c482 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
Dclk-exynos5420.c1127 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
/linux-6.6.21/arch/arm/boot/dts/samsung/
Dexynos5410.dtsi434 clocks = <&clock CLK_WDT>;
Dexynos4210.dtsi300 clocks = <&clock CLK_WDT>;
Dexynos4x12.dtsi312 clocks = <&clock CLK_WDT>;
Ds5pv210.dtsi299 clocks = <&clocks CLK_WDT>;
Dexynos5250.dtsi313 clocks = <&clock CLK_WDT>;
Dexynos5420.dtsi1391 clocks = <&clock CLK_WDT>;