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Searched refs:CLK_TOP_UNIVPLL_D5_D4 (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/include/dt-bindings/clock/
Dmt8183-clk.h106 #define CLK_TOP_UNIVPLL_D5_D4 70 macro
Dmt8186-clk.h111 #define CLK_TOP_UNIVPLL_D5_D4 92 macro
Dmt6779-clk.h81 #define CLK_TOP_UNIVPLL_D5_D4 71 macro
Dmt8192-clk.h105 #define CLK_TOP_UNIVPLL_D5_D4 93 macro
Dmediatek,mt8188-clk.h129 #define CLK_TOP_UNIVPLL_D5_D4 118 macro
Dmt8195-clk.h162 #define CLK_TOP_UNIVPLL_D5_D4 150 macro
/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt8186-topckgen.c46 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
Dclk-mt8183.c62 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
Dclk-mt8188-topckgen.c53 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
Dclk-mt8192.c51 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
Dclk-mt8195-topckgen.c64 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
Dclk-mt6779.c55 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
/linux-6.6.21/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi1349 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1350 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1427 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1428 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1451 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1452 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1475 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1476 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
Dmt8192.dtsi924 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
925 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;