| /linux-6.6.21/include/dt-bindings/clock/ |
| D | mt7986-clk.h | 54 #define CLK_TOP_PWM_SEL 31 macro
|
| D | mt7629-clk.h | 87 #define CLK_TOP_PWM_SEL 77 macro
|
| D | mediatek,mt7981-clk.h | 94 #define CLK_TOP_PWM_SEL 81 macro
|
| D | mt8516-clk.h | 188 #define CLK_TOP_PWM_SEL 156 macro
|
| D | mt7622-clk.h | 72 #define CLK_TOP_PWM_SEL 60 macro
|
| D | mediatek,mt6795-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
|
| D | mt8173-clk.h | 96 #define CLK_TOP_PWM_SEL 86 macro
|
| D | mt6765-clk.h | 156 #define CLK_TOP_PWM_SEL 121 macro
|
| D | mediatek,mt8365-clk.h | 99 #define CLK_TOP_PWM_SEL 89 macro
|
| D | mt2712-clk.h | 133 #define CLK_TOP_PWM_SEL 102 macro
|
| D | mt2701-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
|
| D | mt8192-clk.h | 66 #define CLK_TOP_PWM_SEL 54 macro
|
| /linux-6.6.21/Documentation/devicetree/bindings/pwm/ |
| D | mediatek,mt2712-pwm.yaml | 85 clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
|
| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
|
| D | clk-mt7981-topckgen.c | 303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| D | clk-mt6795-topckgen.c | 460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
|
| D | clk-mt8173-topckgen.c | 539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
|
| D | clk-mt7622.c | 396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| D | clk-mt8516.c | 421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| D | clk-mt7629.c | 471 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| D | clk-mt8167.c | 610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
| D | clk-mt2712.c | 650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
|
| D | clk-mt8365.c | 490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
|
| D | clk-mt8192.c | 673 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
|
| /linux-6.6.21/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
|