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Searched refs:CLK_TOP_MUX_MSDC50_0_HCLK (Results 1 – 4 of 4) sorted by relevance

/linux-6.6.21/include/dt-bindings/clock/
Dmt6797-clk.h26 #define CLK_TOP_MUX_MSDC50_0_HCLK 16 macro
Dmt8183-clk.h43 #define CLK_TOP_MUX_MSDC50_0_HCLK 7 macro
/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt6797.c344 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
Dclk-mt8183.c496 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",