Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 12 of 12) sorted by relevance
| /linux-6.6.21/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 117 #define CLK_TOP_AUD_2_SEL 106 macro
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| D | mt8173-clk.h | 120 #define CLK_TOP_AUD_2_SEL 110 macro
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| D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| D | mt2712-clk.h | 157 #define CLK_TOP_AUD_2_SEL 126 macro
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| D | mt8192-clk.h | 60 #define CLK_TOP_AUD_2_SEL 48 macro
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| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 496 TOP_MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0xb0, 0, 2, 7, 0),
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| D | clk-mt8173-topckgen.c | 585 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
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| D | clk-mt2712.c | 688 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7),
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| D | clk-mt8365.c | 458 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
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| D | clk-mt8192.c | 660 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
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| /linux-6.6.21/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 878 <&topckgen CLK_TOP_AUD_2_SEL>;
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| D | mt8192.dtsi | 979 <&topckgen CLK_TOP_AUD_2_SEL>,
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