Searched refs:CLK_TOP_AUD_1_SEL (Results 1 – 14 of 14) sorted by relevance
| /linux-6.6.21/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 116 #define CLK_TOP_AUD_1_SEL 105 macro
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| D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| D | mt8192-clk.h | 59 #define CLK_TOP_AUD_1_SEL 47 macro
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| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 494 TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0xa0, 24, 2, 31, 0),
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| D | clk-mt8173-topckgen.c | 583 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
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| D | clk-mt2712.c | 686 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31),
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| D | clk-mt8365.c | 456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
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| D | clk-mt8192.c | 658 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
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| D | clk-mt6765.c | 425 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
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| /linux-6.6.21/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 877 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
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| D | mt8192.dtsi | 977 <&topckgen CLK_TOP_AUD_1_SEL>,
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