Searched refs:CLK_TOP_APLL12_DIV7 (Results 1 – 5 of 5) sorted by relevance
| /linux-6.6.21/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.h | 214 CLK_TOP_APLL12_DIV7, enumerator
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| D | mt8192-afe-clk.c | 57 [CLK_TOP_APLL12_DIV7] = "top_apll12_div7",
523 .div_clk_id = CLK_TOP_APLL12_DIV7,
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| /linux-6.6.21/include/dt-bindings/clock/ |
| D | mt8192-clk.h | 162 #define CLK_TOP_APLL12_DIV7 150 macro
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| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt8192.c | 708 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
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| /linux-6.6.21/arch/arm64/boot/dts/mediatek/ |
| D | mt8192.dtsi | 1003 <&topckgen CLK_TOP_APLL12_DIV7>,
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