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Searched refs:CLK_MM_MDP_WROT1 (Results 1 – 12 of 12) sorted by relevance

/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt6797-mm.c46 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
Dclk-mt6795-mm.c46 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
Dclk-mt6779-mm.c54 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
Dclk-mt8173-mm.c49 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
Dclk-mt2712-mm.c57 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
/linux-6.6.21/include/dt-bindings/clock/
Dmediatek,mt6795-clk.h232 #define CLK_MM_MDP_WROT1 13 macro
Dmt6797-clk.h228 #define CLK_MM_MDP_WROT1 14 macro
Dmt8173-clk.h260 #define CLK_MM_MDP_WROT1 13 macro
Dmt6779-clk.h387 #define CLK_MM_MDP_WROT1 47 macro
Dmt2712-clk.h314 #define CLK_MM_MDP_WROT1 13 macro
/linux-6.6.21/Documentation/devicetree/bindings/media/
Dmediatek-mdp.txt92 clocks = <&mmsys CLK_MM_MDP_WROT1>;
/linux-6.6.21/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1060 clocks = <&mmsys CLK_MM_MDP_WROT1>;