Searched refs:CLK_MM_DISP_WDMA1 (Results 1 – 9 of 9) sorted by relevance
| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt6797-mm.c | 55 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
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| D | clk-mt6795-mm.c | 55 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
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| D | clk-mt8173-mm.c | 58 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
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| D | clk-mt2712-mm.c | 66 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
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| /linux-6.6.21/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 241 #define CLK_MM_DISP_WDMA1 22 macro
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| D | mt6797-clk.h | 237 #define CLK_MM_DISP_WDMA1 23 macro
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| D | mt8173-clk.h | 269 #define CLK_MM_DISP_WDMA1 22 macro
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| D | mt2712-clk.h | 323 #define CLK_MM_DISP_WDMA1 22 macro
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| /linux-6.6.21/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 1130 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
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