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Searched refs:CLK_I2S1_8CH_TX (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/include/dt-bindings/clock/
Drockchip,rk3588-cru.h647 #define CLK_I2S1_8CH_TX 632 macro
Drk3568-cru.h469 #define CLK_I2S1_8CH_TX 406 macro
/linux-6.6.21/arch/arm64/boot/dts/rockchip/
Drk3568-lubancat-2.dts220 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3566-roc-pc.dts250 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3568-evb1-v10.dts272 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3568-odroid-m1.dts270 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3566-anbernic-rgxx3.dtsi336 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3566-pinenote.dtsi241 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3566-quartz64-b.dts251 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3568-rock-3a.dts329 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
Drk3566-quartz64-a.dts342 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
/linux-6.6.21/drivers/clk/rockchip/
Dclk-rk3568.c356 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
Dclk-rk3588.c552 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,