Searched refs:CLK_HW_INIT_HW (Results 1 – 14 of 14) sorted by relevance
| /linux-6.6.21/drivers/clk/mmp/ |
| D | clk-audio.c | 264 priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div", in register_clocks()
277 priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk", in register_clocks()
286 priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div", in register_clocks()
298 priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk", in register_clocks()
317 priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div", in register_clocks()
329 priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk", in register_clocks()
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| /linux-6.6.21/drivers/clk/sprd/ |
| D | div.h | 58 _shift, _width, _flags, CLK_HW_INIT_HW)
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| D | pll.h | 116 _fflag, _fvco, CLK_HW_INIT_HW)
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| D | gate.h | 88 CLK_HW_INIT_HW)
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| /linux-6.6.21/drivers/clk/sunxi-ng/ |
| D | ccu_gate.h | 36 .hw.init = CLK_HW_INIT_HW(_name, \
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| D | ccu_div.h | 119 .hw.init = CLK_HW_INIT_HW(_name, \
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| D | ccu-sun6i-rtc.c | 189 .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
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| /linux-6.6.21/drivers/clk/microchip/ |
| D | clk-mpfs-ccc.c | 172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
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| D | clk-mpfs.c | 275 .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
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| /linux-6.6.21/drivers/clk/stm32/ |
| D | clk-stm32mp13.c | 1279 .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
1284 .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
1296 .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
1301 .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
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| /linux-6.6.21/drivers/rtc/ |
| D | rtc-jz4740.c | 409 rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk), in jz4740_rtc_probe()
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| /linux-6.6.21/include/linux/ |
| D | clk-provider.h | 1415 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ macro
1501 .hw.init = CLK_HW_INIT_HW(_name, \
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| /linux-6.6.21/drivers/clk/ |
| D | clk-bm1880.c | 192 .hw.init = CLK_HW_INIT_HW(_name, _parent, \
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| D | clk_test.c | 2196 ctx->hw.init = CLK_HW_INIT_HW("test-clock", &ctx->mux_ctx.hw, in clk_leaf_mux_set_rate_parent_test_init()
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