Home
last modified time | relevance | path

Searched refs:CLK_HW_INIT_HW (Results 1 – 14 of 14) sorted by relevance

/linux-6.6.21/drivers/clk/mmp/
Dclk-audio.c264 priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div", in register_clocks()
277 priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk", in register_clocks()
286 priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div", in register_clocks()
298 priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk", in register_clocks()
317 priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div", in register_clocks()
329 priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk", in register_clocks()
/linux-6.6.21/drivers/clk/sprd/
Ddiv.h58 _shift, _width, _flags, CLK_HW_INIT_HW)
Dpll.h116 _fflag, _fvco, CLK_HW_INIT_HW)
Dgate.h88 CLK_HW_INIT_HW)
/linux-6.6.21/drivers/clk/sunxi-ng/
Dccu_gate.h36 .hw.init = CLK_HW_INIT_HW(_name, \
Dccu_div.h119 .hw.init = CLK_HW_INIT_HW(_name, \
Dccu-sun6i-rtc.c189 .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
/linux-6.6.21/drivers/clk/microchip/
Dclk-mpfs-ccc.c172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
Dclk-mpfs.c275 .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
/linux-6.6.21/drivers/clk/stm32/
Dclk-stm32mp13.c1279 .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
1284 .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
1296 .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
1301 .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
/linux-6.6.21/drivers/rtc/
Drtc-jz4740.c409 rtc->clk32k.init = CLK_HW_INIT_HW("clk32k", __clk_get_hw(clk), in jz4740_rtc_probe()
/linux-6.6.21/include/linux/
Dclk-provider.h1415 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ macro
1501 .hw.init = CLK_HW_INIT_HW(_name, \
/linux-6.6.21/drivers/clk/
Dclk-bm1880.c192 .hw.init = CLK_HW_INIT_HW(_name, _parent, \
Dclk_test.c2196 ctx->hw.init = CLK_HW_INIT_HW("test-clock", &ctx->mux_ctx.hw, in clk_leaf_mux_set_rate_parent_test_init()