| /linux-6.6.21/drivers/clk/mediatek/ ! |
| D | clk-mt8186-apmixedsys.c | 61 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
132 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
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| D | clk-mt6795-apmixedsys.c | 54 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
106 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
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| D | clk-mt8173-apmixedsys.c | 71 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
125 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
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| D | clk-mt8195-apmixedsys.c | 68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
159 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
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| D | clk-mt8192-apmixedsys.c | 79 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
141 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
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| D | clk-mt8135-apmixedsys.c | 43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
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| D | clk-mt8188-apmixedsys.c | 63 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
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| D | clk-mt2712-apmixedsys.c | 96 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
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| D | clk-mt8365-apmixedsys.c | 91 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
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| D | clk-mt8183-apmixedsys.c | 129 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
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| /linux-6.6.21/include/dt-bindings/clock/ ! |
| D | mt8135-clk.h | 113 #define CLK_APMIXED_MSDCPLL 6 macro
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| D | mediatek,mt6795-clk.h | 145 #define CLK_APMIXED_MSDCPLL 4 macro
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| D | mt6797-clk.h | 111 #define CLK_APMIXED_MSDCPLL 4 macro
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| D | mt8173-clk.h | 161 #define CLK_APMIXED_MSDCPLL 6 macro
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| D | mt6765-clk.h | 17 #define CLK_APMIXED_MSDCPLL 7 macro
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| D | mediatek,mt8365-clk.h | 235 #define CLK_APMIXED_MSDCPLL 4 macro
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| D | mt8183-clk.h | 16 #define CLK_APMIXED_MSDCPLL 5 macro
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| D | mt8186-clk.h | 269 #define CLK_APMIXED_MSDCPLL 5 macro
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| D | mt6779-clk.h | 172 #define CLK_APMIXED_MSDCPLL 7 macro
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| D | mt2712-clk.h | 20 #define CLK_APMIXED_MSDCPLL 8 macro
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| D | mt2701-clk.h | 179 #define CLK_APMIXED_MSDCPLL 5 macro
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| D | mt8192-clk.h | 304 #define CLK_APMIXED_MSDCPLL 3 macro
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| D | mediatek,mt8188-clk.h | 301 #define CLK_APMIXED_MSDCPLL 1 macro
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| /linux-6.6.21/Documentation/devicetree/bindings/clock/ ! |
| D | mediatek,mt8186-fhctl.yaml | 56 clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
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| /linux-6.6.21/arch/arm64/boot/dts/mediatek/ ! |
| D | mt6795-sony-xperia-m5.dts | 56 <&apmixedsys CLK_APMIXED_MSDCPLL>;
|