| /linux-6.6.21/arch/arm/mach-omap1/ |
| D | omap-dma.c | 158 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
162 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
200 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
203 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
268 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
271 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
418 p->dma_write(dev_id | (1 << 10), CCR, free_ch); in omap_request_dma()
420 p->dma_write(dev_id, CCR, free_ch); in omap_request_dma()
443 p->dma_write(0, CCR, lch); in omap_free_dma()
510 l = p->dma_read(CCR, lch); in omap_start_dma()
[all …]
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| D | dma.c | 57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
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| /linux-6.6.21/drivers/dma/ |
| D | txx9dmac.h | 77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
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| D | txx9dmac.c | 295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
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| D | pl330.c | 340 CCR, enumerator
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1276 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1425 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
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| /linux-6.6.21/arch/arm/mach-imx/ |
| D | pm-imx6.c | 31 #define CCR 0x0 macro
255 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
258 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
261 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
264 writel(val, ccm_base + CCR); in imx6_enable_rbc()
288 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
291 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
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| /linux-6.6.21/drivers/clocksource/ |
| D | timer-atmel-tcb.c | 104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
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| /linux-6.6.21/drivers/pwm/ |
| D | pwm-atmel-tcb.c | 167 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
172 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
257 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
522 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
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| /linux-6.6.21/include/sound/ |
| D | emu10k1.h | 475 #define CCR 0x09 /* Cache control register */ macro
476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
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| /linux-6.6.21/arch/arm/mach-omap2/ |
| D | dma.c | 54 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
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| /linux-6.6.21/Documentation/translations/zh_CN/arch/parisc/ |
| D | registers.rst | 28 CR10 (CCR) FPU延迟保存*
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| /linux-6.6.21/drivers/counter/ |
| D | microchip-tcb-capture.c | 130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
137 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
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| /linux-6.6.21/drivers/dma/ti/ |
| D | omap-dma.c | 457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
931 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1543 if (omap_dma_chan_read(c, CCR) & CCR_ENABLE) in omap_dma_busy()
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| /linux-6.6.21/sound/soc/intel/keembay/ |
| D | kmb_platform.h | 23 #define CCR 0x010 macro
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| D | kmb_platform.c | 658 writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR); in kmb_dai_hw_params()
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| /linux-6.6.21/sound/soc/dwc/ |
| D | local.h | 24 #define CCR 0x010 macro
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| D | dwc-i2s.c | 324 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
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| /linux-6.6.21/include/linux/ |
| D | omap-dma.h | 153 CSDP, CCR, CICR, CSR, enumerator
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| /linux-6.6.21/Documentation/arch/parisc/ |
| D | registers.rst | 18 CR10 (CCR) lazy FPU saving*
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| /linux-6.6.21/sound/pci/emu10k1/ |
| D | emu10k1_callback.c | 434 CCR, REG_VAL_PUT(CCR_CACHEINVALIDSIZE, 64), in start_voice()
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| D | emu10k1_main.c | 58 CCR, 0, in snd_emu10k1_voice_init()
1744 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
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| D | emupcm.c | 597 snd_emu10k1_ptr_write(emu, CCR, voice + 1, ccr); in snd_emu10k1_playback_fill_cache()
599 snd_emu10k1_ptr_write(emu, CCR, voice, ccr); in snd_emu10k1_playback_fill_cache()
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| /linux-6.6.21/Documentation/powerpc/ |
| D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
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| /linux-6.6.21/drivers/tty/ |
| D | synclink_gt.c | 368 #define CCR 0x89 /* clock control */ macro
3814 wr_reg8(info, CCR, 0x49); in enable_loopback()
4097 wr_reg8(info, CCR, 0x69); in async_mode()
4310 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()
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| /linux-6.6.21/drivers/video/fbdev/ |
| D | imsttfb.c | 94 CCR = 0x00000008L,
|