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Searched refs:C5 (Results 1 – 23 of 23) sorted by relevance

/linux-6.6.21/crypto/
Dwp512.c498 static const u64 C5[256] = { variable
809 C5[(int)(K[3] >> 16) & 0xff] ^ in wp512_process_buffer()
819 C5[(int)(K[4] >> 16) & 0xff] ^ in wp512_process_buffer()
828 C5[(int)(K[5] >> 16) & 0xff] ^ in wp512_process_buffer()
837 C5[(int)(K[6] >> 16) & 0xff] ^ in wp512_process_buffer()
846 C5[(int)(K[7] >> 16) & 0xff] ^ in wp512_process_buffer()
855 C5[(int)(K[0] >> 16) & 0xff] ^ in wp512_process_buffer()
864 C5[(int)(K[1] >> 16) & 0xff] ^ in wp512_process_buffer()
873 C5[(int)(K[2] >> 16) & 0xff] ^ in wp512_process_buffer()
891 C5[(int)(state[3] >> 16) & 0xff] ^ in wp512_process_buffer()
[all …]
/linux-6.6.21/arch/s390/crypto/
Dchacha-s390.S467 #define C5 %v22 macro
519 VLR C5,K2
550 VAF C5,C5,D5
556 VX B5,B5,C5
588 VAF C5,C5,D5
594 VX B5,B5,C5
607 VSLDB C5,C5,C5,8
645 VAF C5,C5,D5
651 VX B5,B5,C5
683 VAF C5,C5,D5
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.yaml128 5: C5
137 5 : C5
159 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
160 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
182 if the platform has one such slot, e.g., x16 slot owned by C5 controller
187 if the platform has one such slot, e.g., x16 slot owned by C5 controller
Dnvidia,tegra194-pcie-ep.yaml20 On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
21 On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
129 5: C5
138 5 : C5
/linux-6.6.21/Documentation/translations/zh_CN/core-api/
Dprotection-keys.rst24 对于任何希望测试或使用该功能的人来说，它在亚马逊的EC2 C5实例中是可用的，
/linux-6.6.21/arch/arm/boot/dts/broadcom/
Dbcm47081-tplink-archer-c5-v2.dts12 model = "TP-LINK Archer C5 V2";
/linux-6.6.21/Documentation/devicetree/bindings/power/
Drenesas,sysc-rmobile.yaml91 // C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP
/linux-6.6.21/arch/m68k/fpsp040/
Dsatan.S408 |--X'+X'*Y*(C1+Y*(C2+Y*(C3+Y*(C4+Y*C5)))), X' = -1/X, Y = X'*X'
440 faddx %fp2,%fp1 | ...[Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)]
/linux-6.6.21/drivers/pinctrl/aspeed/
Dpinctrl-aspeed-g5.c1253 #define C5 168 macro
1254 SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
1255 SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
1256 SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
1257 PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
1258 SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
1267 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
1268 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
1974 ASPEED_PINCTRL_PIN(C5),
Dpinctrl-aspeed-g4.c89 #define C5 4 macro
90 SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
91 SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
92 PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
94 FUNC_GROUP_DECL(TIMER5, C5);
102 FUNC_GROUP_DECL(I2C9, C5, B4);
1980 ASPEED_PINCTRL_PIN(C5),
Dpinctrl-aspeed-g6.c1326 #define C5 212 macro
1327 SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4),
1329 PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2);
1376 FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
1781 ASPEED_PINCTRL_PIN(C5),
/linux-6.6.21/arch/arm64/boot/dts/ti/
Dk3-j7200-som-p0.dtsi95 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
Dk3-am62x-sk-common.dtsi281 AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
Dk3-am62-verdin.dtsi766 AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */
/linux-6.6.21/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra194-pinmux.yaml75 are part of PCIE C5 power partition. Client devices must
/linux-6.6.21/arch/arm/boot/dts/aspeed/
Daspeed-bmc-tyan-s7106.dts458 /*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */
/linux-6.6.21/Documentation/arch/arm64/
Dcpu-feature-registers.rst97 (See Table C5-6 'System instruction encodings for non-Debug System
/linux-6.6.21/arch/sparc/kernel/
Dtraps_64.c1091 #define C5 133 macro
1102 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
/linux-6.6.21/tools/arch/x86/kcpuid/
Dcpuid.csv119 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
/linux-6.6.21/
DCREDITS506 P: 512/71EC9367 C5 29 0F BC 83 51 B9 F0 BC 05 89 A0 4F 1F 30 05
2040 P: 1024/3BC8D885 8C 29 C5 0A C0 D1 D6 F4 20 D4 2D AB 29 F6 D0 60
4258 P: 1024/E298966D F0 37 4F FD E5 7E C5 E6 F1 A0 1E 22 6F 46 DA 0C
/linux-6.6.21/arch/m68k/ifpsp060/src/
Dfplsp.S6413 #--X'+X'*Y*( [C1+Z*(C3+Z*C5)] + [Y*(C2+Z*C4)] ), Z = Y*Y.
6432 fmul.x %fp1,%fp3 # Z*C5
6435 fadd.d ATANC3(%pc),%fp3 # C3+Z*C5
6438 fmul.x %fp3,%fp1 # Z*(C3+Z*C5), FP3 RELEASED
6441 fadd.d ATANC1(%pc),%fp1 # C1+Z*(C3+Z*C5)
Dfpsp.S6517 #--X'+X'*Y*(C1+Y*(C2+Y*(C3+Y*(C4+Y*C5)))), X' = -1/X, Y = X'*X'
6550 fadd.x %fp2,%fp1 # [Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)]
/linux-6.6.21/Documentation/networking/
Darcnet-hardware.rst101 cabling (Type1, Fiber, C1, C4, C5).