Searched refs:BANK_HEIGHT (Results 1 – 15 of 15) sorted by relevance
85 #define BANK_HEIGHT(x) ((x) << 16) macro410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()[all …]
74 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) macro2196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v8_0_tiling_mode_table_init()2216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v8_0_tiling_mode_table_init()2228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()[all …]
1123 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v7_0_tiling_mode_table_init()1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1139 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v7_0_tiling_mode_table_init()1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()[all …]
195 # define BANK_HEIGHT(x) ((x) << 2) macro
1208 # define BANK_HEIGHT(x) ((x) << 16) macro
1942 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1911 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1986 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
2036 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()2584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()[all …]
2437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2449 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()[all …]
1211 # define BANK_HEIGHT(x) ((x) << 16) macro
1265 # define BANK_HEIGHT(x) ((x) << 2) macro
188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
1755 typedef enum BANK_HEIGHT { enum1760 } BANK_HEIGHT; typedef