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Searched refs:ASID (Results 1 – 20 of 20) sorted by relevance

/linux-6.6.21/arch/arm/include/asm/
Dmmu.h27 #define ASID(mm) ((unsigned int)((mm)->context.id.counter & ~ASID_MASK)) macro
29 #define ASID(mm) (0) macro
Dtlbflush.h363 const int asid = ASID(mm); in __local_flush_tlb_mm()
381 const int asid = ASID(mm); in local_flush_tlb_mm()
405 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm)); in __flush_tlb_mm()
418 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __local_flush_tlb_page()
439 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in local_flush_tlb_page()
456 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __flush_tlb_page()
/linux-6.6.21/arch/arm/mm/
Dtlb-v7.S40 asid r3, r3 @ mask ASID
49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
Dtlb-v6.S42 asid r3, r3 @ mask ASID
DKconfig610 This indicates whether the CPU has the ASID register; used to
/linux-6.6.21/arch/arm64/include/asm/
Dtlbflush.h252 asid = __TLBI_VADDR(0, ASID(mm)); in flush_tlb_mm()
265 addr = __TLBI_VADDR(uaddr, ASID(mm)); in __flush_tlb_page_nosync()
428 asid = ASID(vma->vm_mm); in __flush_tlb_range()
Dmmu.h56 #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) macro
Dmmu_context.h224 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
/linux-6.6.21/arch/loongarch/include/asm/
Dhw_breakpoint.h54 #define LOONGARCH_CSR_NAME_ASID ASID
/linux-6.6.21/Documentation/ABI/testing/
Ddebugfs-driver-habanalabs216 Description: Displays the hop values and physical address for a given ASID
217 and virtual address. The user should write the ASID and VA into
219 e.g. to display info about VA 0x1000 for ASID 1 you need to do:
317 address mappings per ASID and all user mappings of HW blocks
/linux-6.6.21/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.yaml84 The ASID number associated to the context bank.
/linux-6.6.21/arch/loongarch/kernel/
Dhw_breakpoint.c74 GEN_READ_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val); in read_wb_reg()
89 GEN_WRITE_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val); in write_wb_reg()
/linux-6.6.21/arch/arm64/mm/
Dcontext.c352 unsigned long asid = ASID(mm); in cpu_do_switch_mm()
/linux-6.6.21/arch/arm/
DKconfig727 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
731 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
736 entries regardless of the ASID.
770 bool "ARM errata: possible faulty MMU translations following an ASID switch"
775 which starts prior to an ASID switch but completes afterwards. This
777 the new ASID. This workaround places two dsb instructions in the mm
778 switching code so that no page table walks can cross the ASID switch.
845 which sends an IPI to the CPUs that are running the same ASID
/linux-6.6.21/Documentation/translations/zh_CN/arch/loongarch/
Dintroduction.rst112 0x18 地址空间标识符 ASID
/linux-6.6.21/tools/arch/x86/kcpuid/
Dcpuid.csv450 0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-en…
451 0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabl…
/linux-6.6.21/arch/arm64/
DKconfig1117 contains data for a non-current ASID. The fix is to
1180 bool "Falkor E1003: Incorrect translation due to ASID change"
1183 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1184 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1606 zeroed area and reserved ASID. The user access routines
/linux-6.6.21/Documentation/virt/kvm/x86/
Damd-memory-encryption.rst46 Hence, the ASID for the SEV-enabled guests must be from 1 to a maximum value
/linux-6.6.21/Documentation/arch/loongarch/
Dintroduction.rst115 0x18 Address Space Identifier ASID
/linux-6.6.21/arch/arm64/tools/
Dsysreg2413 Field 63:48 ASID