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Searched refs:xge_wr_csr (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/net/ethernet/apm/xgene-v2/
Denet.c12 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val) in xge_wr_csr() function
32 xge_wr_csr(pdata, ENET_CLKEN, 0x3); in xge_port_reset()
33 xge_wr_csr(pdata, ENET_SRST, 0xf); in xge_port_reset()
34 xge_wr_csr(pdata, ENET_SRST, 0); in xge_port_reset()
35 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 1); in xge_port_reset()
36 xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 0); in xge_port_reset()
48 xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH); in xge_port_reset()
57 xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1); in xge_traffic_resume()
58 xge_wr_csr(pdata, FORCE_LINK_STATUS, 1); in xge_traffic_resume()
60 xge_wr_csr(pdata, CFG_LINK_AGGR_RESUME, 1); in xge_traffic_resume()
[all …]
Dmac.c14 xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET); in xge_mac_reset()
15 xge_wr_csr(pdata, MAC_CONFIG_1, 0); in xge_mac_reset()
58 xge_wr_csr(pdata, MAC_CONFIG_2, mc2); in xge_mac_set_speed()
59 xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl); in xge_mac_set_speed()
60 xge_wr_csr(pdata, RGMII_REG_0, rgmii); in xge_mac_set_speed()
61 xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0); in xge_mac_set_speed()
62 xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2); in xge_mac_set_speed()
63 xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0); in xge_mac_set_speed()
75 xge_wr_csr(pdata, STATION_ADDR0, addr0); in xge_mac_set_station_addr()
76 xge_wr_csr(pdata, STATION_ADDR1, addr1); in xge_mac_set_station_addr()
[all …]
Dring.c39 xge_wr_csr(pdata, DMATXDESCL, dma_addr); in xge_update_tx_desc_addr()
40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr()
51 xge_wr_csr(pdata, DMARXDESCL, dma_addr); in xge_update_rx_desc_addr()
52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
63 xge_wr_csr(pdata, DMAINTRMASK, data); in xge_intr_enable()
68 xge_wr_csr(pdata, DMAINTRMASK, 0); in xge_intr_disable()
Dmdio.c20 xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); in xge_mdio_write()
22 xge_wr_csr(pdata, MII_MGMT_CONTROL, data); in xge_mdio_write()
44 xge_wr_csr(pdata, MII_MGMT_ADDRESS, val); in xge_mdio_read()
46 xge_wr_csr(pdata, MII_MGMT_COMMAND, MII_READ_CYCLE); in xge_mdio_read()
58 xge_wr_csr(pdata, MII_MGMT_COMMAND, 0); in xge_mdio_read()
Dmain.c220 xge_wr_csr(pdata, DMATXCTRL, 1); in xge_start_xmit()
274 xge_wr_csr(pdata, DMATXSTATUS, 1); in xge_txc_poll()
336 xge_wr_csr(pdata, DMARXSTATUS, 1); in xge_rx_poll()
337 xge_wr_csr(pdata, DMARXCTRL, 1); in xge_rx_poll()
485 xge_wr_csr(pdata, DMARXCTRL, 1); in xge_open()
591 xge_wr_csr(pdata, DMATXCTRL, 0); in xge_timeout()
594 xge_wr_csr(pdata, DMATXSTATUS, ~0U); in xge_timeout()
Denet.h28 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val);