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Searched refs:wm_table (Results 1 – 19 of 19) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.h33 extern struct wm_table ddr4_wm_table_gs;
34 extern struct wm_table lpddr4_wm_table_gs;
35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;
36 extern struct wm_table ddr4_wm_table_rn;
37 extern struct wm_table ddr4_1R_wm_table_rn;
38 extern struct wm_table lpddr4_wm_table_rn;
Drn_clk_mgr.c462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
677 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
680 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
684 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in rn_clk_mgr_helper_populate_bw_params()
685 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
750 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; in rn_clk_mgr_construct()
753 rn_bw_params.wm_table = lpddr4_wm_table_gs; in rn_clk_mgr_construct()
755 rn_bw_params.wm_table = lpddr4_wm_table_rn; in rn_clk_mgr_construct()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
371 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
372 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
401 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
406 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
407 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
408 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_fpu_calculate_wm_and_dlg()
448 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_fpu_calculate_wm_and_dlg()
462 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c180 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
182 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
188 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
189 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
190 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
191 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()
193 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn32_build_wm_range_table_fpu()
194 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
195 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.h32 extern struct wm_table ddr4_wm_table;
33 extern struct wm_table lpddr5_wm_table;
Dvg_clk_mgr.c396 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
586 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
589 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
593 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()
594 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
708 vg_bw_params.wm_table = lpddr5_wm_table; in vg_clk_mgr_construct()
710 vg_bw_params.wm_table = ddr4_wm_table; in vg_clk_mgr_construct()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c277 static struct wm_table ddr4_wm_table = {
314 static struct wm_table lpddr5_wm_table = {
363 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
366 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
367 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
558 bw_params->wm_table.entries[i].wm_inst = i; in dcn316_clk_mgr_helper_populate_bw_params()
561 bw_params->wm_table.entries[i].valid = false; in dcn316_clk_mgr_helper_populate_bw_params()
565 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn316_clk_mgr_helper_populate_bw_params()
566 bw_params->wm_table.entries[i].valid = true; in dcn316_clk_mgr_helper_populate_bw_params()
679 dcn316_bw_params.wm_table = lpddr5_wm_table; in dcn316_clk_mgr_construct()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c341 static struct wm_table ddr5_wm_table = {
378 static struct wm_table lpddr5_wm_table = {
427 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
430 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
615 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
618 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
622 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()
623 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()
727 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_clk_mgr.c285 static struct wm_table ddr5_wm_table = {
322 static struct wm_table lpddr5_wm_table = {
371 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
375 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
574 bw_params->wm_table.entries[i].wm_inst = i; in dcn315_clk_mgr_helper_populate_bw_params()
577 bw_params->wm_table.entries[i].valid = false; in dcn315_clk_mgr_helper_populate_bw_params()
581 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn315_clk_mgr_helper_populate_bw_params()
582 bw_params->wm_table.entries[i].valid = true; in dcn315_clk_mgr_helper_populate_bw_params()
661 dcn315_bw_params.wm_table = lpddr5_wm_table; in dcn315_clk_mgr_construct()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/
Ddcn301_fpu.c218 struct wm_table ddr4_wm_table = {
255 struct wm_table lpddr5_wm_table = {
431 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg_fp()
439 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_calculate_wm_and_dlg_fp()
444 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_calculate_wm_and_dlg_fp()
450 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_calculate_wm_and_dlg_fp()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c360 static struct wm_table ddr5_wm_table = {
397 static struct wm_table lpddr5_wm_table = {
446 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
694 bw_params->wm_table.entries[i].wm_inst = i; in dcn314_clk_mgr_helper_populate_bw_params()
697 bw_params->wm_table.entries[i].valid = false; in dcn314_clk_mgr_helper_populate_bw_params()
701 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn314_clk_mgr_helper_populate_bw_params()
702 bw_params->wm_table.entries[i].valid = true; in dcn314_clk_mgr_helper_populate_bw_params()
777 dcn314_bw_params.wm_table = lpddr5_wm_table; in dcn314_clk_mgr_construct()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h215 struct wm_table { struct
234 struct wm_table wm_table; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c342 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn3_notify_wm_ranges()
343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
345 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
346 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
348 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.c456 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
457 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
458 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
467 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
474 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c657 struct wm_table ddr4_wm_table_gs = {
694 struct wm_table lpddr4_wm_table_gs = {
731 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
768 struct wm_table ddr4_wm_table_rn = {
805 struct wm_table ddr4_1R_wm_table_rn = {
842 struct wm_table lpddr4_wm_table_rn = {
2013 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
2020 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
2031 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
2126 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr.c615 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn32_notify_wm_ranges()
617 …table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_bre… in dcn32_notify_wm_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c2532 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local
2537 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
Dvega20_hwmgr.c3644 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local
3649 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
Dvega10_hwmgr.c4909 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local
4914 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()