/linux-6.1.9/sound/pci/emu10k1/ |
D | emu10k1.c | 91 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local 165 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe() 166 wave == NULL) { in snd_card_emu10k1_probe() 171 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe() 172 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
|
/linux-6.1.9/sound/pci/ |
D | ad1889.c | 90 struct ad1889_register_state wave; member 190 chip->wave.reg = reg; in ad1889_channel_reset() 358 chip->wave.size = size; in snd_ad1889_playback_prepare() 359 chip->wave.reg = reg; in snd_ad1889_playback_prepare() 360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare() 362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare() 368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); in snd_ad1889_playback_prepare() 379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare() 460 chip->wave.reg = wsmc; in snd_ad1889_playback_trigger() 516 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) in snd_ad1889_playback_pointer() [all …]
|
/linux-6.1.9/Documentation/devicetree/bindings/rtc/ |
D | maxim,ds3231.txt | 14 - 0: square-wave output on the SQW pin 15 - 1: square-wave output on the 32kHz pin
|
D | rtc-m41t80.txt | 25 - clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
|
D | nxp,pcf85063.yaml | 42 Provide this if the square wave pin is used as boot-enabled
|
/linux-6.1.9/sound/pci/au88x0/ |
D | au88x0.c | 267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in __snd_vortex_probe() 268 || wave == NULL) { in __snd_vortex_probe() 273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in __snd_vortex_probe() 274 strcpy(wave->name, "Aureal Synth"); in __snd_vortex_probe()
|
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v9_4_2.c | 422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local 439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment() 456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local 468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned() 469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned() 1825 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument 1828 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 1839 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local 1851 wave = i % cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status() 1853 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status() [all …]
|
D | gfx_v6_0.c | 2959 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument 2962 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 2970 uint32_t wave, uint32_t thread, in wave_read_regs() argument 2974 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 2984 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v6_0_read_wave_data() argument 2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data() 2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data() 2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data() 2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data() 2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data() [all …]
|
D | amdgpu_gfx.h | 220 uint32_t wave, uint32_t *dst, int *no_fields); 222 uint32_t wave, uint32_t thread, uint32_t start, 225 uint32_t wave, uint32_t start, uint32_t size,
|
D | gfx_v7_0.c | 4122 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument 4125 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 4133 uint32_t wave, uint32_t thread, in wave_read_regs() argument 4137 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 4147 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument 4151 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data() 4152 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data() 4153 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data() 4154 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data() 4155 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data() [all …]
|
D | amdgpu_debugfs.c | 883 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local 893 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read() 914 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read() 975 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local 985 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read() 1008 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read() 1011 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
|
D | gfx_v11_0.c | 765 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument 768 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 773 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument 778 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 786 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v11_0_read_wave_data() argument 795 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v11_0_read_wave_data() 796 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v11_0_read_wave_data() 797 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v11_0_read_wave_data() 798 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v11_0_read_wave_data() 799 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v11_0_read_wave_data() [all …]
|
D | gfx_v9_0.c | 1825 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument 1828 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 1836 uint32_t wave, uint32_t thread, in wave_read_regs() argument 1840 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 1850 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v9_0_read_wave_data() argument 1854 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data() 1855 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data() 1856 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data() 1857 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data() 1858 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data() [all …]
|
D | gfx_v8_0.c | 5219 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument 5222 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 5230 uint32_t wave, uint32_t thread, in wave_read_regs() argument 5234 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 5244 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v8_0_read_wave_data() argument 5248 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data() 5249 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data() 5250 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data() 5251 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data() 5252 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data() [all …]
|
D | gfx_v10_0.c | 4350 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument 4353 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind() 4358 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument 4363 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs() 4371 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument 4380 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data() 4381 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data() 4382 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data() 4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data() 4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data() [all …]
|
/linux-6.1.9/Documentation/devicetree/bindings/clock/ti/davinci/ |
D | pll.txt | 18 - ti,clkmode-square-wave: Indicates that the board is supplying a square 19 wave input on the OSCIN pin instead of using a crystal oscillator. 61 ti,clkmode-square-wave;
|
/linux-6.1.9/drivers/gpu/ipu-v3/ |
D | ipu-dc.c | 120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument 129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl() 132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
|
/linux-6.1.9/Documentation/devicetree/bindings/clock/ |
D | nvidia,tegra124-dfll.txt | 56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
|
/linux-6.1.9/Documentation/virt/kvm/x86/ |
D | timekeeping.rst | 103 This generates a high / low square wave. The count 112 which generates sine-like tones by low-pass filtering the square wave output. 253 bit 3 = Square wave interrupt enable
|
/linux-6.1.9/drivers/media/rc/ |
D | Kconfig | 344 wave and pulses.
|
/linux-6.1.9/Documentation/driver-api/media/drivers/ |
D | vidtv.rst | 34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.
|