Searched refs:wait_reg_mem (Results 1 – 3 of 3) sorted by relevance
317 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; in mes_v11_0_misc_op()318 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()319 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()320 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()321 misc_pkt.wait_reg_mem.reg_offset2 = 0; in mes_v11_0_misc_op()325 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; in mes_v11_0_misc_op()326 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()327 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()328 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()329 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
828 struct radeon_cs_packet p3reloc, wait_reg_mem; in r600_cs_common_vline_parse() local837 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()842 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || in r600_cs_common_vline_parse()843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()875 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()880 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
571 struct WAIT_REG_MEM wait_reg_mem; member